ADuM1200/ADuM1201
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the
entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent IDDI (Q)
0.50
0.19
0.60
0.25
mA
mA
Output Supply Current, per Channel, Quiescent
ADuM1200, Total Supply Current, Two Channels1
DC to 2 Mbps
IDDO (Q)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.1
0.5
1.4
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.3
1.3
5.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (25)
IDD2 (25)
10
2.8
13
3.4
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
ADuM1201, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
0.8
0.8
1.1
1.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
2.8
2.8
3.5
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (25)
IDD2 (25)
6.3
6.3
8.0
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
IIA, IIB
VIH
VIL
−10
0.7 VDD1, VDD2
+0.01 +10
µA
V
V
0 ≤ VIA, VIB ≤ VDD1 or VDD2
0.3 VDD1,
VDD2
Logic High Output Voltages
VOAH
VOBH
VDD1
DD2 − 0.1
VDD1
VDD2 − 0.5
,
5.0
4.8
V
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
V
,
Logic Low Output Voltages
VOAL
VOBL
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
Mbps
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
Propagation Delay4
tPHL, tPLH 50
PWD
tPSK
tPSKCD/OD
tR/tF
150
40
100
50
4
Pulse-Width Distortion, |tPLH − tPHL
|
Propagation Delay Skew5
Channel-to-Channel Matching6
ns
ns
Output Rise/Fall Time (10% to 90%)
10
Rev. B | Page 3 of 20
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