ADuC832
Parameter
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
SCLOCK and RESET Only4
(Schmitt-Triggered Inputs)
VT+
1.3
3.0
0.8
1.4
0.3
0.85
0.95
2.5
0.4
1.1
0.3
V min
V max
V min
V max
V min
V max
VT–
VT+ – VT–
0.85
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Input Capacitance
XTAL2 Output Capacitance
0.8
3.5
18
0.4
2.5
18
V typ
V typ
pF typ
pF typ
18
18
MCU CLOCK RATE
DIGITAL OUTPUTS
Output High Voltage (VOH
16.78
16.78
MHz max
Programmable via PLLCON
VDD = 4.5 V to 5.5 V
)
2.4
4.0
V min
V typ
V min
V typ
I
SOURCE = 80 µA
2.4
2.6
VDD = 2.7 V to 3.3 V
ISOURCE = 20 µA
Output Low Voltage (VOL
ALE, Ports 0 and 2
)
0.4
0.2
0.4
0.4
0.4
0.2
0.4
0.4
V max
V typ
V max
V max
ISINK = 1.6 mA
ISINK = 1.6 mA
Port 3
SCLOCK/SDATA
I
SINK = 4 mA
ISINK = 8 mA, I2C Enabled
Floating State Leakage Current4
10
1
10
10
1
10
µA max
µA typ
pF typ
Floating State Output Capacitance
START UP TIME
At Power-On
From Idle Mode
At any Core CLK
500
100
500
100
ms typ
µs typ
From Power-Down Mode
Wakeup with INT0 Interrupt
Wakeup with SPI/I2C Interrupt
Wakeup with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
150
150
150
30
400
400
400
30
µs typ
µs typ
µs typ
ms typ
ms typ
3
3
Controlled via WDCON SFR
REV. 0
–5–