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ADUC7023BCP6Z62I-RL PDF预览

ADUC7023BCP6Z62I-RL

更新时间： 2024-01-18 01:15:01
品牌 Logo 应用领域
亚德诺 - ADI 微控制器
页数 文件大小 规格书
96页 1473K
描述
IC RISC MICROCONTROLLER, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40, Microcontroller

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ADUC7023BCP6Z62I-RL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40针数：40
Reach Compliance Code：unknown风险等级：5.32
具有ADC：YES地址总线宽度：
位大小：32最大时钟频率：44 MHz
DAC 通道：YESDMA 通道：NO
外部数据总线宽度：JESD-30 代码：S-XQCC-N40
长度：6 mmI/O 线路数量：20
端子数量：40最高工作温度：125 °C
最低工作温度：-40 °CPWM 通道：YES
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
ROM可编程性：FLASH座面最大高度：0.8 mm
速度：41.78 MHz最大供电电压：3.6 V
最小供电电压：2.7 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLER, RISCBase Number Matches：1

ADUC7023BCP6Z62I-RL 数据手册

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Data Sheet  
ADuC7023  
Parameter  
Min  
Typ  
Max  
Unit  
kHz  
%
Test Conditions/Comments  
INTERNAL OSCILLATOR  
32.768  
3
MCU CLOCK RATE  
From 32 kHz Internal Oscillator  
From 32 kHz External Crystal  
Using an External Clock  
326  
41.78  
kHz  
CD = 7  
CD = 0  
TA = 85°C  
TA = 125°C  
Core clock = 41.78 MHz  
MHz  
MHz  
MHz  
0.05  
0.05  
44  
41.78  
START-UP TIME  
At Power-On  
From Pause/Nap Mode  
66  
24  
ms  
ns  
CD = 0  
CD = 7  
3.07  
1.58  
1.7  
µs  
ms  
ms  
From Sleep Mode  
From Stop Mode  
PROGRAMMABLE LOGIC ARRAY (PLA)  
Pin Propagation Delay  
12  
2.5  
ns  
ns  
From input pin to output pin  
Element Propagation Delay  
POWER REQUIREMENTS14, 15  
Power Supply Voltage Range  
AVDD to AGND and IOVDD to DGND  
Analog Power Supply Currents  
AVDD Current  
2.7  
3.6  
V
200  
µA  
ADC in idle mode  
Digital Power Supply Current  
IOVDD Current in Normal Mode  
Code executing from Flash/EE  
CD = 7  
CD = 3  
CD = 0 (41.78 MHz clock)  
CD = 0 (41.78 MHz clock)  
8.5  
11  
28  
14  
10  
15  
35  
20  
mA  
mA  
mA  
mA  
IOVDD Current in Pause Mode  
IOVDD Current in Sleep Mode  
230  
650  
µA  
TA = 125°C  
Additional Power Supply Currents  
ADC  
1.4  
0.7  
400  
mA  
mA  
µA  
At 1 MSPS  
At 62.5 kSPS  
Per DAC  
DAC  
ESD TESTS  
2.5 V reference, TA = 25°C  
HBM Passed  
FICDM Passed  
3
kV  
kV  
1.0  
1 All ADC channel specifications are guaranteed during normal microcontroller core operation.  
2 Apply to all ADC input channels.  
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).  
4 Not production tested but supported by design and/or characterization data on production release.  
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC  
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).  
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.  
7 DAC linearity is calculated using a reduced code range of 100 to 3995.  
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF  
9 DAC linearity is calculated using a reduced code range of 100 to 3995.  
.
10 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF  
.
11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.  
12 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.  
13 Test carried out with a maximum of eight I/Os set to a low output level.  
14 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with  
3.6 V supply, and sleep mode with 3.6 V supply.  
15 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.  
Rev. E | Page 7 of 96  
 
1...45678910...96

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