ADT14
(V+ = +5 V, GND = 0 V, TA = +25؇C unless otherwise noted)
WAFER TEST LIMITS
Parameter
Symbol
Conditions
Min
Typ Max
Units
INPUTS SET HIGH, SET LOW
Input Bias Current
IB
70
nA
°C
V
OUTPUT VPTAT
Temperature Accuracy
TA = +25°C, No Load
1.5
OUTPUT VREF
Nominal Value
Line Regulation
Load Regulation
VREF
TA = +25°C, No Load
4.5 V ≤ V ≤ 13.2 V
10 µA ≤ IVREF ≤ 500 µA
2.490
2.510
±0.08 %/V
±0.25 %/mA
OPEN-COLLECTOR OUTPUTS OVER, UNDER
Output Low Voltage
Output Leakage Current
VOL
IOH
ISINK = 1.6 mA
0.4
100
V
µA
POWER SUPPLY
Supply Range
Supply Current
V+
ISY
4.5
5.5
600
V
µA
Unloaded
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly and nominal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on lot qualification through sample lot assembly and testing.
DICE CHARACTERISTICS
Die Size 0.069 × 0.080 inch, 5520 sq. mils
(1.75 × 2.03 mm, 3.55 sq. mm)
Transistor Count: 130
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADT14 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–