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ADSP-21483KSWZ-4B PDF预览

ADSP-21483KSWZ-4B

更新时间: 2024-01-02 14:03:50
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
68页 1778K
描述
SHARC Processor

ADSP-21483KSWZ-4B 技术参数

Source Url Status Check Date:2013-05-01 14:56:48.727是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
零件包装代码:QFP包装说明:LQFP-176
针数:176Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.77Is Samacsys:N
地址总线宽度:24位大小:40
边界扫描:YES最大时钟频率:25 MHz
外部数据总线宽度:16格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-PQFP-G176
长度:24 mm低功率模式:NO
端子数量:176最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HLFQFP封装等效代码:QFP176,1.0SQ,20
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.1,3.3 V
认证状态:Not QualifiedRAM(字数):98304
座面最大高度:1.6 mm速度:400 MHz
子类别:Digital Signal Processors最大供电电压:1.15 V
最小供电电压:1.05 V标称供电电压:1.1 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24 mm
uPs/uCs/外围集成电路类型:MICROPROCESSORBase Number Matches:1

ADSP-21483KSWZ-4B 数据手册

 浏览型号ADSP-21483KSWZ-4B的Datasheet PDF文件第4页浏览型号ADSP-21483KSWZ-4B的Datasheet PDF文件第5页浏览型号ADSP-21483KSWZ-4B的Datasheet PDF文件第6页浏览型号ADSP-21483KSWZ-4B的Datasheet PDF文件第8页浏览型号ADSP-21483KSWZ-4B的Datasheet PDF文件第9页浏览型号ADSP-21483KSWZ-4B的Datasheet PDF文件第10页 
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489  
Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)1  
IOP Registers 0x0000 0000–0x0003 FFFF  
Extended Precision Normal or  
Long Word (64 Bits)  
Instruction Word (48 Bits)  
Normal Word (32 Bits)  
Short Word (16 Bits)  
Block 0 ROM (Reserved)  
Block 0 ROM (Reserved)  
Block 0 ROM (Reserved)  
Block 0 ROM (Reserved)  
0x0004 0000–0x0004 7FFF  
0x0008 0000–0x0008 AAA9  
0x0008 0000–0x0008 FFFF  
0x0010 0000–0x0011 FFFF  
Reserved  
Reserved  
Reserved  
Reserved  
0x0004 8000–0x0004 8FFF  
0x0008 AAAA–0x0008 BFFF  
0x0009 0000–0x0009 1FFF  
0x0012 0000–0x0012 3FFF  
Block 0 SRAM  
Block 0 SRAM  
Block 0 SRAM  
Block 0 SRAM  
0x0004 9000–0x0004 EFFF  
0x0008 C000–0x0009 3FFF  
0x0009 2000–0x0009 DFFF  
0x0012 4000–0x0013 BFFF  
Reserved  
Reserved  
Reserved  
Reserved  
0x0004 F000–0x0004 FFFF  
0x0009 4000–0x0009 FFFF  
0x0009 E000–0x0009 FFFF  
0x0013 C000–0x0013 FFFF  
Block 1 ROM (Reserved)  
Block 1 ROM (Reserved)  
Block 1 ROM (Reserved)  
Block 1 ROM (Reserved)  
0x0005 0000–0x0005 7FFF  
0x000A 0000–0x000A AAA9  
0x000A 0000–0x000A FFFF  
0x0014 0000–0x0015 FFFF  
Reserved  
Reserved  
Reserved  
Reserved  
0x0005 8000–0x0005 8FFF  
0x000A AAAA–0x000A BFFF  
0x000B 0000–0x000B 1FFF  
0x0016 0000–0x0016 3FFF  
Block 1 SRAM  
Block 1 SRAM  
Block 1 SRAM  
Block 1 SRAM  
0x0005 9000–0x0005 EFFF  
0x000A C000–0x000B 3FFF  
0x000B 2000–0x000B DFFF  
0x0016 4000–0x0017 BFFF  
Reserved  
Reserved  
Reserved  
Reserved  
0x0005 F000–0x0005 FFFF  
0x000B 4000–0x000B FFFF  
0x000B E000–0x000B FFFF  
0x0017 C000–0x0017 FFFF  
Block 2 SRAM  
Block 2 SRAM  
Block 2 SRAM  
Block 2 SRAM  
0x0006 0000–0x0006 3FFF  
0x000C 0000–0x000C 5554  
0x000C 0000–0x000C 7FFF  
0x0018 0000–0x0018 FFFF  
Reserved  
Reserved  
Reserved  
Reserved  
0x0006 4000– 0x0006 FFFF  
0x000C 5555–0x000D FFFF  
0x000C 8000–0x000D FFFF  
0x0019 0000–0x001B FFFF  
Block 3 SRAM  
Block 3 SRAM  
Block 3 SRAM  
Block 3 SRAM  
0x0007 0000–0x0007 3FFF  
0x000E 0000–0x000E 5554  
0x000E 0000–0x000E 7FFF  
0x001C 0000–0x001C FFFF  
Reserved  
Reserved  
Reserved  
Reserved  
0x0007 4000–0x0007 FFFF  
0x000E 5555–0x0000F FFFF  
0x000E 8000–0x000F FFFF  
0x001D 0000–0x001F FFFF  
1 Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Please contact your Analog Devices sales representative  
for additional details.  
instruction that retrieves 48-bit memory. The 32-bit section  
describes what this address range looks like to an instruction  
that retrieves 32-bit memory.  
FAMILY PERIPHERAL ARCHITECTURE  
The ADSP-2148x family contains a rich set of peripherals that  
support a wide variety of applications including high quality  
audio, medical imaging, communications, military, test equip-  
ment, 3D graphics, speech recognition, motor control, imaging,  
and other applications.  
ROM Based Security  
The ADSP-2148x has a ROM security feature that provides  
hardware support for securing user software code by preventing  
unauthorized reading from the internal code. When using this  
feature, the processor does not boot-load any external code, exe-  
cuting exclusively from internal ROM. Additionally, the  
processor is not freely accessible via the JTAG port. Instead, a  
unique 64-bit key, which must be scanned in through the JTAG  
or Test Access Port will be assigned to each customer. The  
device will ignore a wrong key. Emulation features are available  
after the correct key is scanned.  
External Memory  
The external port interface supports access to the external mem-  
ory through core and DMA accesses. The external memory  
address space is divided into four banks. Any bank can be pro-  
grammed as either asynchronous or synchronous memory. The  
external ports are comprised of the following modules.  
• An Asynchronous Memory Interface which communicates  
with SRAM, FLASH, and other devices that meet the stan-  
dard asynchronous SRAM access protocol. The AMI  
supports 6M words of external memory in bank 0 and 8M  
words of external memory in bank 1, bank 2, and bank 3.  
On-Chip Memory Bandwidth  
The internal memory architecture allows programs to have four  
accesses at the same time to any of the four blocks (assuming  
there are no block conflicts). The total bandwidth is realized  
using the DMD and PMD buses (2 × 64-bits, CCLK speed) and  
the IOD0/1 buses (2 × 32-bit, PCLK speed).  
• A SDRAM controller that supports a glueless interface with  
any of the standard SDRAMs. The SDC supports 62M  
words of external memory in bank 0, and 64M words of  
external memory in bank 1, bank 2, and bank 3. NOTE: this  
feature is not available on the ADSP-21486 product.  
Rev. B  
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Page 7 of 68  
|
March 2013  

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