Datasheet > ADSP-2111BS-66

ADSP-2111BS-66

更新时间： 2024-02-10 13:24:56

品牌	Logo	应用领域
亚德诺 - ADI		计算机
页数	文件大小	规格书
64页	666K
描述
ADSP-2100 Family DSP Microcomputers

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技术参数
数据手册

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ADSP-2111BS-66 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.A.3	HTS代码：	8542.31.00.01
风险等级：	5.66	其他特性：	20 MIPS; 8/16 BIT PARALLEL HOST INTERFACE PORT; SINGLE CYCLE INSTRUCTION EXECUTION
地址总线宽度：	14	桶式移位器：	YES
位大小：	16	边界扫描：	NO
最大时钟频率：	16.67 MHz	外部数据总线宽度：	24
格式：	FIXED POINT	集成缓存：	NO
内部总线架构：	MULTIPLE	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0	长度：	19.05 mm
低功率模式：	YES	DMA 通道数量：
外部中断装置数量：	1	串行 I/O 数：	2
端子数量：	100	计时器数量：	1
片上数据RAM宽度：	16	片上程序ROM宽度：
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	SPQFP100,.9SQ	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	5 V	认证状态：	Not Qualified
RAM（字数）：	1000	座面最大高度：	4.572 mm
子类别：	Digital Signal Processors	最大压摆率：	52 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT APPLICABLE	宽度：	19.05 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

ADSP-2111BS-66 数据手册

ADSP-21xx

T he interrupt force and clear register, IFC, is a write-only

rupt (except for level-sensitive interrupts and the ADSP-2111

HIP interrupts—these cannot be forced or cleared in software).

SYSTEM INTERFACE

Figure 3 shows a typical system for the ADSP-2101, ADSP-

2115, or ADSP-2103, with two serial I/O devices, a boot

EPROM, and optional external program and data memory. A

total of 15K words of data memory and 16K words of program

memory is addressable for the ADSP-2101 and ADSP-2103. A

total of 14.5K words of data memory and 15K words of

program memory is addressable for the ADSP-2115.

When responding to an interrupt, the AST AT , MST AT , and

IMASK status registers are pushed onto the status stack and

the PC counter is loaded with the appropriate vector address.

T he status stack is seven levels deep (nine levels deep on the

ADSP-2111) to allow interrupt nesting. T he stack is automati-

cally popped when a return from the interrupt instruction is

executed.

Figure 4 shows a system diagram for the ADSP-2105, with one

serial I/O device, a boot EPROM, and optional external

program and data memory. A total of 14.5K words of data

memory and 15K words of program memory is addressable for

the ADSP-2105.

P in D efinitions

T able IV (on next page) shows pin definitions for the ADSP-

21xx processors. Any inputs not used must be tied to V_DD

Figure 5 shows a system diagram for the ADSP-2111, with two

serial I/O devices, a host processor, a boot EPROM, and

optional external program and data memory. A total of 15K

words of data memory and 16K words of program memory is

addressable.

Table III. Interrupt Vector Addresses & P riority

AD SP -2105

Interrupt

Source

Interrupt

Vector Address

Programmable wait-state generation allows the processors to

easily interface to slow external memories.

RESET Startup

IRQ2

SPORT 1 T ransmit or IRQ1

SPORT 1 Receive or IRQ0

T imer

0x0000

0x0004 (High Priority)

0x0010

0x0014

0x0018 (Low Priority)

T he ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111

processors also provide either: one external interrupt (IRQ2)

and two serial ports (SPORT 0, SPORT 1), or three external

interrupts (IRQ2, IRQ1, IRQ0) and one serial port (SPORT 0).

T he ADSP-2105 provides either: one external interrupt (IRQ2)

and one serial port (SPORT 1), or three external interrupts

(IRQ2, IRQ1, IRQ0) with no serial port.

AD SP -2101/2103/2115/216x

Interrupt

Source

Vector Address

Clock Signals

T he ADSP-21xx processors’ CLKIN input may be driven by a

crystal or by a T T L-compatible external clock signal. T he

CLKIN input may not be halted or changed in frequency during

operation, nor operated below the specified low frequency limit.

RESET Startup

IRQ2

0x0000

0x0004 (High Priority)

0x0008

0x000C

0x0010

SPORT 0 T ransmit

SPORT 0 Receive

SPORT 1 T ransmit or IRQ1

SPORT 1 Receive or IRQ0

T imer

If an external clock is used, it should be a T T L-compatible

signal running at the instruction rate. T he signal should be

connected to the processor’s CLKIN input; in this case, the

XT AL input must be left unconnected.

0x0014

0x0018 (Low Priority)

AD SP -2111

Interrupt

Source

Because the ADSP-21xx processors include an on-chip oscilla-

tor circuit, an external crystal may also be used. T he crystal

should be connected across the CLKIN and XT AL pins, with

two capacitors connected as shown in Figure 2. A parallel-

resonant, fundamental frequency, microprocessor-grade crystal

should be used.

Interrupt

Vector Address

RESET Startup

IRQ2

0x0000

0x0004 (High Priority)

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020 (Low Priority)

HIP Write from Host

HIP Read to Host

SPORT 0 T ransmit

SPORT 0 Receive

SPORT 1 T ransmit or IRQ1

SPORT 1 Receive or IRQ0

T imer

XTAL

ADSP-21xx

CLKIN

CLKOUT

Figure 2. External Crystal Connections

REV. B

–7–

1...4 5 678 9 10...64

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与ADSP-2111BS-66相关器件

型号	品牌	描述	获取价格	数据表
ADSP-2111BS-80	ADI	ADSP-2100 Family DSP Microcomputers	获取价格
ADSP-2111BS-80	ROCHESTER	Digital Signal Processor, 24-Ext Bit, 20MHz, CMOS, PQFP100, METRIC, PLASTIC, QFP-100	获取价格
ADSP-2111KG-52	ROCHESTER	24-BIT, 13MHz, OTHER DSP, CPGA100, CERAMIC, PGA-100	获取价格
ADSP-2111KG-52	ADI	ADSP-2100 Family DSP Microcomputers	获取价格
ADSP-2111KG-66	ADI	ADSP-2100 Family DSP Microcomputers	获取价格
ADSP-2111KG-80	ADI	ADSP-2100 Family DSP Microcomputers	获取价格

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