ADP3307
THEORY OF OPERATION
This is no longer true with the ADP3307 anyCAP LDO. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. The innovative design allows the
circuit to be stable with just a small 0.47 µF capacitor on the
output. Additional advantages of the design scheme include
superior line noise rejection and very high regulator gain that
lead to excellent line and load regulation. An impressive 1.4%
accuracy is guaranteed over line, load and temperature.
The ADP3307 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
Q1
OUTPUT
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard solu-
tions that give warning after the output has lost regulation, the
ADP3307 provides improved system performance by enabling
the ERR pin to give warning before the device loses regulation.
COMPENSATION
CAPACITOR
ATTENUATION R1
(V
/V
)
BANDGAP OUT
R3 D1
PTAT
V
(a)
NONINVERTING
WIDEBAND
DRIVER
R
OS
gm
LOAD
PTAT
CURRENT
As the chip’s temperature rises above 165°C, the circuit acti-
vates a soft thermal shutdown, indicated by a signal low on the
ERR pin, to reduce the current to a safe level.
R4
R2
ADP3307
C
LOAD
To reduce the noise gain of the loop, the node of the main
divider network (a) is made available at the noise reduction
(NR) pin which can be bypassed with a small capacitor
(10 nF–100 nF).
GND
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset volt-
age” that is repeatable and very well controlled. The gained up
temperature proportional offset voltage is combined with the diode
voltage to form a “virtual bandgap” voltage, implicit in the net-
work, although it never appears explicitly in the circuit. Ultimately,
this patented design makes it possible to control the loop with
only one amplifier. This technique also improves the noise char-
acteristics of the amplifier by providing more flexibility on the
trade-off of noise sources that leads to a low noise design.
APPLICATION INFORMATION
Capacitor Selection: anyCAP
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance.
The ADP3307 is stable with a wide range of capacitor values,
types and ESR (anyCAP). A capacitor as low as 0.47 µF is all
that is needed for stability. However, larger capacitors can be
used if high output current surges are anticipated. There is an
upper limit on the size of the output capacitor. The ADP3307
is stable with extremely low ESR capacitors (ESR ≈ 0), such as
multilayer ceramic capacitors (MLCC) or OSCON.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1, and a second divider consist-
ing of R3 and R4, the values are chosen to produce a tempera-
ture stable output.
Input Bypass Capacitor: an input bypass capacitor is not required;
however, for applications where the input source is high impedance
or far from the input pins, a bypass capacitor is recommended.
Connecting a 0.47 µF capacitor from the input to ground reduces
the circuit’s sensitivity to PC board layout. If a bigger output
capacitor is used, the input capacitor should be 1 µF minimum.
The patented amplifier controls a new and unique noninvert-
ing driver that drives the pass transistor, Q1. The use of this
special noninverting driver enables the frequency compensa-
tion to include the load capacitor in a pole splitting arrange-
ment to achieve reduced sensitivity to the value, type and ESR
of the load capacitance.
Noise Reduction
A noise reduction capacitor (CNR) can be used to further reduce
the noise by 6 dB–10 dB (Figure 3). Low leakage capacitors in
10 nF–100 nF range provide the best performance. As the noise
reduction capacitor increases the high frequency loop-gain of
the regulator, the circuit requires a larger output capacitor if it is
used. The recommended value is 4.7 µF, as shown in Figure 3.
Since the noise reduction pin (NR) is internally connected to a
high impedance node, any connection to this node should be
carefully done to avoid noise pick up from external sources. The
pad connected to this pin should be as small as possible. Long
PC board traces are not recommended.
Most LDOs place strict requirements on the range of ESR val-
ues for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value, required to keep conventional LDOs
stable, changes depending on load and temperature. These
ESR limitations make designing with conventional LDOs more
difficult because of their unclear specifications and the depen-
dence of ESR over temperature.
–6–
REV. A
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