5秒后页面跳转
捷配首页

Datasheet > ADP3302AR-3.0
ADP3302AR-3.0 PDF预览

ADP3302AR-3.0

更新时间： 2024-01-29 13:57:47
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管输出元件调节器
页数 文件大小 规格书
8页 302K
描述
IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO8, SOP-8, Fixed Positive Multiple Output LDO Regulator

阅读下载

获取价格

ADP3302AR-3.0 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP-8针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.69
最大输入电压：22 V最小输入电压：3 V
JESD-30 代码：R-PDSO-G8长度：4.9 mm
功能数量：1输出次数：2
端子数量：8工作温度TJ-Max：125 °C
工作温度TJ-Min：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
调节器类型：FIXED POSITIVE MULTIPLE OUTPUT LDO REGULATOR座面最大高度：1.75 mm
表面贴装：YES端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

ADP3302AR-3.0 数据手册

 浏览型号ADP3302AR-3.0的Datasheet PDF文件第2页浏览型号ADP3302AR-3.0的Datasheet PDF文件第3页浏览型号ADP3302AR-3.0的Datasheet PDF文件第4页浏览型号ADP3302AR-3.0的Datasheet PDF文件第5页浏览型号ADP3302AR-3.0的Datasheet PDF文件第6页浏览型号ADP3302AR-3.0的Datasheet PDF文件第7页 
ADP3302  
2.5V → 4.2V  
(SUMIDA–CDRH62)  
R5  
330kΩ  
R1  
100kΩ  
R4  
120kΩ  
L1  
6.6µF  
Q1  
2N2907  
100µF  
10V  
AVX-TPS  
IN5817  
C1  
I
V
3V  
100mA  
LIM  
IN  
V
O2  
IN  
IN  
R6  
100kΩ  
R8  
10kΩ  
1µF  
6V  
(MLC)  
C3  
100µF  
10V  
SET  
C4  
C5  
SW1  
R9  
348kΩ  
1%  
C2  
33nF  
R3  
1MΩ  
ADP3302  
R7  
90kΩ  
ADP3000  
FB  
AVX-TPS  
1µF  
6V  
R2  
A
O
90kΩ  
(MLC)  
SD  
R10  
200kΩ  
1%  
3V  
100mA  
V
O2  
GND SW2  
GND  
Figure 20. Cell Li-Ion to 3 V/200 mA Converter with Shutdown at VIN < 2.5 V  
Phase One: When the input voltage is equal to 3.7 V or higher,  
the ADP3000 is off and the ADP3302 operates on its own to  
regulate the output voltage. At this phase, current is flowing into  
the input pins of the ADP3302 via the inductor L1 and the  
Schottky diode. At the same time, the ADP3000 is set into sleep  
mode by pulling the FB pin (via R9 and R10 resistor divider  
network) to about 10% higher than its internal reference which  
is set to be 1.245 V.  
Supply Sequencing Circuit  
Figure 22 shows a simple and effective way to achieve sequenc-  
ing of two different output voltages, 3.3 V and 5 V, in a mixed  
supply voltage system. In most cases, these systems need careful  
sequencing for the supplies to avoid latchup.  
At turn-on, D1 rapidly charges up C1 and enables the 5 V out-  
put. After a R2-C2 time constant delay, the 3.3 V output is  
enabled. At turn-off, D2 quickly discharges C2 and R3 pulls  
SD1 low, turning off the 3.3 V output first. After a R1-C1 time  
constant delay, the 5 V output turns off.  
Phase Two: As the input voltage drops below 3.7 V, the  
decreasing input voltage causes the voltage of the FB pin to be  
within 5% of the 1.245 V reference. This triggers the ADP3000  
to turn on, providing a 3.4 V regulated output to the inputs of  
the ADP3302. The ADP3000 continues to supply the 3.4 V  
regulated voltage to the ADP3302 until the input voltage drops  
below 2.5 V.  
2
V
= 6V TO 12V  
IN  
ERR  
OUT1  
8
5
IN  
IN  
V
C5  
OUT1  
3.3V  
1
4
1µF  
C3  
0.5µF  
D3  
D2  
D1  
7
SD1  
C2  
0.01µF  
R3  
330kΩ  
ADP3302  
Phase Three: When the input voltage drops below 2.5 V, the  
ADP3302 will shut down and the ADP3000 will go into sleep  
mode. With the input voltage below 2.5 V, the resistor divider  
network, R1 and R2, applies a voltage that is lower than the  
ADP3000’s internal 1.245 V reference voltage to the SET pin.  
This causes the AO pin to have a voltage close to 0 V, which  
causes the ADP3302 to go into shutdown directly and Q1 to  
turn on and pull the FB pin 10% or higher than the internal  
1.245 V reference voltage. With the FB pin pulled high, the  
ADP3000 goes into sleep mode.  
3.3V  
ON/OFF  
V
OUT2  
5.0V  
OUT2  
6
C4  
0.5µF  
SD2  
C1  
0.01µF  
GND  
3
R2  
220kΩ  
R1  
220kΩ  
Figure 22. Turn-On/Turn-Off Sequencing for Mixed Supply  
Voltages  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
AT V ≤ 2.5V  
SHDN IQ = 500µA  
IN  
80  
75  
70  
65  
I
= 50mA + 50mA  
O
8-Pin SOIC  
(SO-8)  
0.1968 (5.00)  
0.1890 (4.80)  
I
= 100mA + 100mA  
O
8
1
5
4
V
IN  
(V)  
0.1574 (4.00)  
0.1497 (3.80)  
0.2440 (6.20)  
0.2284 (5.80)  
2.6  
3.0  
3.4  
3.8  
4.2  
Figure 21. Typical Efficiency of the Circuit of Figure 20  
PIN 1  
0.0688 (1.75)  
0.0532 (1.35)  
0.0196 (0.50)  
0.0099 (0.25)  
x 45°  
0.0098 (0.25)  
0.0040 (0.10)  
Refer to Figure 20. R9 and R10 set the output voltage of the  
ADP3000. R1, R2, and R3 set the shutdown threshold voltage  
for the circuit. For further details on the ADP3000, please refer  
to the ADP3000 data sheet.  
8°  
0°  
0.0500  
(1.27)  
BSC  
0.0192 (0.49)  
0.0138 (0.35)  
SEATING  
PLANE  
0.0098 (0.25)  
0.0075 (0.19)  
0.0500 (1.27)  
0.0160 (0.41)  
REV. 0  
–8–  
1...5678

下载PDF

与ADP3302AR-3.0相关器件

型号 品牌 描述 获取价格 数据表
ADP3302AR-3.2 ROCHESTER DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO8, SOP-8

获取价格
ADP3302AR-3.3 ADI IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO8, SOP-8, Fixed Positive Multiple O

获取价格
ADP3302AR3-REEL ADI IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO8, SOIC-8, Fixed Positive Multiple

获取价格
ADP3302AR4 ADI High Precision anyCAP⑩ Dual Low Dropout Linea

获取价格
ADP3302AR4-REEL ADI 暂无描述

获取价格
ADP3302AR5 ADI High Precision anyCAP⑩ Dual Low Dropout Linea

获取价格

与ADP3302AR-3.0相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证