Datasheet > ADP2166ACPZ-2.5-R7

ADP2166ACPZ-2.5-R7

更新时间： 2024-01-05 05:34:03

品牌	Logo	应用领域
亚德诺 - ADI		开关
页数	文件大小	规格书
23页	695K
描述
5.5 V, 6 A, High Efficiency, Step-Down DC-to-DC Regulators with Output Tracking

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ADP2166ACPZ-2.5-R7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	24	Reach Compliance Code：	compliant
风险等级：	5.7	模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE	控制技术：	PULSE WIDTH MODULATION
最大输入电压：	5.5 V	最小输入电压：	2.7 V
标称输入电压：	5 V	JESD-30 代码：	S-XQCC-N24
长度：	4 mm	功能数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-40 °C	标称输出电压：	2.5 V
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度：	0.8 mm	表面贴装：	YES
切换器配置：	BUCK	最大切换频率：	1400 kHz
温度等级：	AUTOMOTIVE	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	4 mm	Base Number Matches：	1

ADP2166ACPZ-2.5-R7 数据手册

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Data Sheet

ADP2165/ADP2166

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SYNC

PVIN

ADP2165/

ADP2166

TRK

TOP VIEW

(Not to Scale)

COMP

PGND

NOTES

1. EXPOSED PAD. SOLDER THE EXPOSED

PAD TO AN EXTERNAL GROUND PLANE

UNDERNEATH THE IC FOR THERMAL

DISSIPATION.

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

SYNC

Synchronization Input. Connect this pin to an external clock between 250 kHz and 1.4 MHz to synchronize the

switching frequency to the external clock. RT can be used to program the phase shift when synchronizing the

external clock.

Frequency Setting. Connect a resistor between the RT and GND pins to program the switching frequency between

250 kHz to 1.4 MHz. When the RT pin is floating, the frequency is set to 620 kHz, and when the RT pin is connected

to VREG, the frequency is set to 1.2 MHz.

TRK

Tracking Input. This pin can be used for tracking and sequencing. If the tracking function is not used, connect TRK

to VREG.

COMP

GND

PGOOD

BST

Soft Start Control. Connect a capacitor from the SS pin to the GND pin to program the soft start time.

Error Amplifier Output. Connect a compensation network from the COMP pin to the GND pin.

Feedback Voltage Sense Input. Connect to a resistor divider from V_OUT

Analog Ground. Connect to the ground plane.

Power-Good Output (Open-Drain). A pull-up resistor of 100 kΩ is recommended.

Supply Rail for the High-Side MOSFET Gate Drive. Place a 0.1 µF capacitor between the SW pin and the BST pin.

Power Ground. Connect this pin to the ground plane and to the output return side of the output capacitor.

10, 11,

12, 13

PGND

14, 15,

16, 17

Switching Node.

18, 19,

20, 21

PVIN

AVIN

Power Input. Connect this pin to the input power source and connect a bypass capacitor between this pin and

ground.

Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND and a small (10 Ω) resistor between

this pin and PVIN.

Precision Enable Input Pin. An external resistor divider can be used to set the turn-on threshold. To enable the

device automatically, connect the EN pin to PVIN. This pin has a 1 MΩ pull-down resistor to GND.

Internal Bias Regulator Output. It supplies the regulated voltage to the internal circuitry. Bypass the VREG pin to

the GND pin with a high quality, low ESR 1 µF ceramic capacitor.

VREG

EPAD

Exposed Pad. Solder the exposed pad to an external ground plane underneath the IC for thermal dissipation.

Rev. B | Page 7 of 23

1...4 5 678 9 10...23

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