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ADP1713AUJZ-0.9-R7 PDF预览

ADP1713AUJZ-0.9-R7

更新时间: 2024-02-05 09:46:44
品牌 Logo 应用领域
亚德诺 - ADI 稳压器
页数 文件大小 规格书
16页 491K
描述
300 mA, Low Dropout CMOS Linear Regulator

ADP1713AUJZ-0.9-R7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSOT
包装说明:VSSOP, TSOP5/6,.11,37针数:5
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.84
可调性:FIXED最大回动电压 1:0.27 V
最大绝对输入电压:6 V最大输入电压:5.5 V
最小输入电压:2.5 VJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2.9 mm
最大电网调整率:0.0092%最大负载调整率:0.0104%
湿度敏感等级:1功能数量:1
输出次数:1端子数量:5
工作温度TJ-Max:125 °C工作温度TJ-Min:-40 °C
最大输出电流 1:0.3 A最大输出电压 1:0.918 V
最小输出电压 1:0.882 V标称输出电压 1:0.9 V
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified调节器类型:FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度:1 mm子类别:Other Regulators
表面贴装:YES技术:CMOS
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40最大电压容差:2%
宽度:1.6 mmBase Number Matches:1

ADP1713AUJZ-0.9-R7 数据手册

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ADP1712/ADP1713/ADP1714  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
1
2
3
5
1
2
3
5
1
2
3
5
4
1
2
3
5
4
IN  
GND  
EN  
OUT  
IN  
GND  
EN  
OUT  
IN  
GND  
EN  
OUT  
BYP  
IN  
GND  
EN  
OUT  
TRK  
ADP1712  
ADP1712  
ADP1713  
ADP1714  
ADJUSTABLE  
FIXED  
TOP VIEW  
(Not to Scale)  
TOP VIEW  
(Not to Scale)  
TOP VIEW  
(Not to Scale)  
TOP VIEW  
(Not to Scale)  
4
4
SS  
ADJ  
Figure 5. 5-Lead TSOT (UJ-Suffix)  
Figure 6. 5-Lead TSOT (UJ-Suffix)  
Figure 7. 5-Lead TSOT (UJ-Suffix)  
Figure 8. 5-Lead TSOT (UJ-Suffix)  
Table 4. Pin Function Descriptions  
ADP1712 ADP1712  
Fixed  
Pin No.  
Adjustable ADP1713 ADP1714  
Pin No.  
Pin No.  
Pin No.  
Mnemonic Description  
1
2
3
1
2
3
1
2
3
1
2
3
IN  
GND  
EN  
Regulator Input Supply. Bypass IN to GND with a 2.2 μF or greater capacitor.  
Ground.  
Enable Input. Drive EN high to turn on the regulator; drive it low to turn  
off the regulator. For automatic startup, connect EN to IN.  
4
5
SS  
Soft Start. Connect a capacitor between SS and GND to set the output  
start-up time.  
Adjust. A resistor divider from OUT to ADJ sets the output voltage.  
Bypass. Connect a 1 nF or greater capacitor (10 nF recommended)  
between BYP and GND to reduce the internal reference noise for low  
noise applications.  
Track. The output follows the voltage placed on the TRK pin. (See the  
Theory of Operation section for a more detailed description.)  
4
5
ADJ  
BYP  
4
5
4
5
TRK  
OUT  
Regulated Output Voltage. Bypass OUT to GND with a 2.2 μF or greater  
capacitor.  
Rev. A | Page 6 of 16  
 

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