Datasheet > ADP1706ARDZ-25-R7

ADP1706ARDZ-25-R7

更新时间： 2022-07-15 11:27:37

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
20页	563K
描述
1 A, Low Dropout, CMOS Linear Regulator

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ADP1706/ADP1707/ADP1708

Parameter

Symbol

Test Conditions

Min

Typ Max

Unit

μV rms

OUTPUT NOISE

OUT_NOISE

10 Hz to 100 kHz, V_OUT= 0.75 V

10 Hz to 100 kHz, V_OUT= 3.3 V

1 kHz, V_OUT= 0.75 V

125

450

POWER SUPPLY REJECTION RATIO

PSRR

1 kHz, V_OUT= 3.3 V

¹Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances

of resistors used.

²Based on an end-point calculation using 10 mA and 1 A loads. See Figure 11 for typical load regulation performance for loads less than 10 mA.

³Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.5 V.

⁴Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value.

⁵Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.

Rev. 0 | Page 4 of 20

1 2 345 6 7...20

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