ADP1652
Preliminary Technical Data
ADP1652—SPECIFICATIONS (SPECIFICATIONS ARE PRELIMINARY AND SUBJECT TO CHANGE)
Table 1. (VDD = 3.6V @TA = -40oC to +85oC, unless otherwise noted.)1
Parameters
Conditions
Min
2.8
Typ
Max
5.0
Units
V
VDD Input Voltage Range (Note 2)
VDD Undervoltage Lockout Threshold
VDD Undervoltage Lockout Hysteresis
VDD Shutdown Current
VDD rising
2.6
2.7
2.8
V
200
mV
μA
μA
mA
EN = GND
1
VDD Operating Current
EN = VDD, ILED Register = 0, HPLED Register = 0
EN = VDD, ILED Register = 1, HPLED Register = 0
40
1
EN = VDD, ILED Register = 0x1, HPLED Register =
0x1, VHPLED = 0.4V (Not Switching)
EN =VDD, ILED Register = 0x1, HPLED Register =
0x1, VHPLED = 0.35V (Step-Up On)
3
mA
LX Leakage
0.5
0.5
μA
HPLED Leakage
μA
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
SYNC Input Frequency
TJ Rising
155
10
°C
°C
SYNC Register = 01 (¼ Frequency Divider)
SYNC Register = 10 (1/8 Frequency Divider)
SYNC Register = 11 (1/16 Frequency Divider)
Time required to sense a logic high
4.0
4.8
9.6
19.2
5.6
11.2
26
MHz
MHz
MHz
ns
8.0
16.0
SYNC Setup Time
10
SDA, SCL, SYNC, STR, EN, GPIO1, GPIO2 Input
Logic Low Threshold
-0.4
1.2
0..4
mV
SDA, SCL, SYNC, STR, EN, GPIO1, GPIO2 Input
Logic High Threshold
VDD +
0.5
V
INT, GPIO1, GPIO2 Logic Low Output Voltage
Isink = --3mA
0.4
1
V
INT, GPIO1, GPIO2, SDA Logic High Leakage
Current
0.1
3
μA
SDA, SCL Input Capacitance
I2C Interface
8
pF
SCL Frequency
0
400
kHz
μs
ns
μs
μs
ns
ns
ns
ns
ns
STOP to START Bus Free Time
Repeated Start Hold Time
SCL Low Period
1.3
600
1.3
0.6
600
After this period, first clock pulse is generated
SCL High Period
50
Repeated Start Setup Time
Data Hold Time
900
300
Data Setup Time
100
600
SDA, SCL Rise Time, Fall Time
Stop Setup Time
Indicator LED
ILED On-State Current
ILED Setting = 1
2.2
16
2.5
2.8
19
1
mA
mA
μA
ILED Setting = 7
17.5
0.01
ILED Off-State Leakage Current
VILED = 5V, ILED Register = 0
Rev. PrB | Page 2 of 13