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ADP122ACPZ-2.0-R7 PDF预览

ADP122ACPZ-2.0-R7

更新时间： 2024-01-24 15:49:56
品牌 Logo 应用领域
亚德诺 - ADI 稳压器
页数 文件大小 规格书
24页 611K
描述
5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator

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ADP122ACPZ-2.0-R7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：2 X 2 MM, ROHS COMPLIANT, LFCSP-6针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.66
最大回动电压 1：0.15 V最大输入电压：5.5 V
最小输入电压：2.3 VJESD-30 代码：S-PDSO-N6
JESD-609代码：e4长度：2 mm
湿度敏感等级：1功能数量：1
端子数量：6工作温度TJ-Max：125 °C
工作温度TJ-Min：-40 °C最大输出电流 1：0.3 A
最大输出电压 1：2.04 V最小输出电压 1：1.96 V
标称输出电压 1：2 V封装主体材料：PLASTIC/EPOXY
封装代码：HVSON封装形状：SQUARE
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR座面最大高度：0.65 mm
表面贴装：YES技术：CMOS
端子面层：NICKEL PALLADIUM GOLD端子形式：NO LEAD
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：2 mm
Base Number Matches：1

ADP122ACPZ-2.0-R7 数据手册

 浏览型号ADP122ACPZ-2.0-R7的Datasheet PDF文件第1页浏览型号ADP122ACPZ-2.0-R7的Datasheet PDF文件第2页浏览型号ADP122ACPZ-2.0-R7的Datasheet PDF文件第3页浏览型号ADP122ACPZ-2.0-R7的Datasheet PDF文件第5页浏览型号ADP122ACPZ-2.0-R7的Datasheet PDF文件第6页浏览型号ADP122ACPZ-2.0-R7的Datasheet PDF文件第7页 
ADP122/ADP123  
Data Sheet  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
25  
35  
45  
55  
65  
60  
60  
60  
60  
60  
60  
Max  
Unit  
µV rms  
µV rms  
µV rms  
µV rms  
µV rms  
dB  
dB  
dB  
dB  
dB  
OUTPUT NOISE  
OUTNOISE  
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.2 V  
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V  
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 2.5 V  
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 3.3 V  
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 4.2 V  
10 kHz, VOUT = 3.3 V  
10 kHz, VOUT = 2.5 V  
10 kHz, VOUT = 1.8 V  
100 kHz, VOUT = 3.3 V  
100 kHz, VOUT = 2.5 V  
POWER SUPPLY REJECTION RATIO  
(VIN = VOUT + 0.5 V)  
PSRR  
100 kHz, VOUT = 1.8 V  
dB  
1 The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP123) should be subtracted from the ground current measured.  
2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of  
the resistors used.  
3 Based on an endpoint calculation using 1 mA and 300 mA loads.  
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages  
greater than 2.3 V.  
5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.  
6 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V  
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3V, or 2.97 V.  
RECOMMENDED SPECIFICATIONS  
Table 2.  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Unit  
Minimum Input and Output  
Capacitance1  
CAPMIN  
TA = −40°C to +125°C  
0.70  
µF  
Capacitor ESR  
RESR  
TA = −40°C to +125°C  
0.001  
1
Ω
1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the  
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;  
Y5V and Z5U capacitors are not recommended for use with any LDO.  
Rev. E | Page 4 of 24  
 
 
 
 
 
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