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ADP120-ACBZ33R7 PDF预览

ADP120-ACBZ33R7

更新时间： 2024-02-02 13:05:29
品牌 Logo 应用领域
亚德诺 - ADI 线性稳压器IC调节器电源电路输出元件
页数 文件大小 规格书
20页 539K
描述
100 mA, Low Quiescent Current, CMOS Linear Regulator

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ADP120-ACBZ33R7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：0.40 MM PITCH, ROHS COMPLIANT, WLCSP-4针数：4
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
Is Samacsys：N可调性：FIXED
最大回动电压 1：0.12 V标称回动电压 1：0.06 V
最大绝对输入电压：6 V最大输入电压：5.5 V
最小输入电压：2.3 VJESD-30 代码：S-PBGA-B4
JESD-609代码：e3长度：0.82 mm
最大电网调整率：0.0018%湿度敏感等级：1
功能数量：1输出次数：1
端子数量：4工作温度TJ-Max：125 °C
工作温度TJ-Min：-40 °C最大输出电流 1：0.1 A
最大输出电压 1：3.325 V最小输出电压 1：3.275 V
标称输出电压 1：3.3 V封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA4,2X2,16
封装形状：SQUARE封装形式：GRID ARRAY
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：225
认证状态：Not Qualified调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：0.66 mm子类别：Other Regulators
表面贴装：YES技术：CMOS
端子面层：MATTE TIN端子形式：BALL
端子节距：0.4 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED最大电压容差：2.5%
宽度：0.82 mmBase Number Matches：1

ADP120-ACBZ33R7 数据手册

 浏览型号ADP120-ACBZ33R7的Datasheet PDF文件第2页浏览型号ADP120-ACBZ33R7的Datasheet PDF文件第3页浏览型号ADP120-ACBZ33R7的Datasheet PDF文件第4页浏览型号ADP120-ACBZ33R7的Datasheet PDF文件第6页浏览型号ADP120-ACBZ33R7的Datasheet PDF文件第7页浏览型号ADP120-ACBZ33R7的Datasheet PDF文件第8页 
ADP120  
ABSOLUTE MAXIMUM RATINGS  
Table 3.  
Junction-to-ambient thermal resistance (θJA) of the package is  
based on modeling and calculation using a four-layer board.  
The junction-to-ambient thermal resistance is highly dependent  
on the application and board layout. In applications where high  
maximum power dissipation exists, close attention to thermal  
board design is required. The value of θJA may vary, depending on  
PCB material, layout, and environmental conditions. The speci-  
fied values of θJA are based on a four-layer, 4 in. × 3 in. PCB.  
Refer to JESD 51-7 and JESD 51-9 for detailed information  
regarding board construction. For additional information, see  
Application Note AN-617, MicroCSPTM Wafer Level Chip Scale  
Package.  
Parameter  
Rating  
VIN to GND Pins  
VOUT to GND Pins  
−0.3 V to +6 V  
−0.3 V to VIN  
EN to GND Pins  
−0.3 V to +6 V  
−65°C to +150°C  
−40°C to +125°C  
JEDEC J-STD-020  
Storage Temperature Range  
Operating Junction Temperature Range  
Soldering Conditions  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Ψ
JB is the junction-to-board thermal characterization parameter  
with units of °C/W. ΨJB of the package is based on modeling and  
calculation using a four-layer board. JESD51-12, Guidelines for  
Reporting and Using Package Thermal Information, states that  
thermal characterization parameters are not the same as  
thermal resistances. ΨJB measures the component power flowing  
through multiple thermal paths rather than a single path as in  
thermal resistance, θJB. Therefore, ΨJB thermal paths include  
convection from the top of the package as well as radiation from  
the package, factors that make ΨJB more useful in real-world  
applications. Maximum junction temperature (TJ) is calculated  
from the board temperature (TB) and power dissipation (PD)  
using the formula  
THERMAL DATA  
Absolute maximum ratings apply individually only, not in  
combination. The ADP120 can be damaged when the junction  
temperature limits are exceeded. Monitoring ambient temperature  
does not guarantee that TJ is within the specified temperature  
limits. In applications with high power dissipation and poor  
thermal resistance, the maximum ambient temperature may  
have to be derated.  
In applications with moderate power dissipation and low PCB  
thermal resistance, the maximum ambient temperature can  
exceed the maximum limit as long as the junction temperature  
is within specification limits. The junction temperature (TJ) of  
the device is dependent on the ambient temperature (TA), the  
power dissipation of the device (PD), and the junction-to-ambient  
thermal resistance of the package (θJA).  
TJ = TB + (PD × ΨJB)  
Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed  
information about ΨJB.  
THERMAL RESISTANCE  
θJA and ΨJB are specified for the worst-case conditions, that is, a  
device soldered in a circuit board for surface-mount packages.  
Maximum junction temperature (TJ) is calculated from the  
ambient temperature (TA) and power dissipation (PD) using the  
formula  
Table 4. Thermal Resistance  
Package Type  
θJA  
ΨJB  
43  
58  
Unit  
°C/W  
°C/W  
TJ = TA + (PD × θJA)  
5-Lead TSOT  
4-Ball, 0.4 mm Pitch WLCSP  
170  
260  
ESD CAUTION  
Rev. A | Page 5 of 20  
 
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