Infineon-ADMtek Co. Ltd.
V1.04
3.8
Jabber Function................................................................................................3-7
3.9
Link Test Function...........................................................................................3-7
Automatic Link Polarity Detection..............................................................3-8
Clock Synthesizer ........................................................................................3-8
Auto Negotiation..........................................................................................3-8
Memory Block .............................................................................................3-8
Switch Functional Description.....................................................................3-9
Basic Operation............................................................................................3-9
3.10
3.11
3.12
3.13
3.14
3.15
3.15.1
3.15.2
Address Learning.....................................................................................3-9
Address Recognition and Packet Forwarding.......................................3-10
Address Aging........................................................................................3-10
Back off Algorithm.................................................................................3-10
Inter-Packet Gap (IPG) .........................................................................3-10
Illegal Frames........................................................................................3-11
Half Duplex Flow Control .....................................................................3-11
Full Duplex Flow Control......................................................................3-11
Broadcast Storm filter............................................................................3-11
3.15.3
3.15.4
3.15.5
3.15.6
3.15.7
3.15.8
3.15.9
3.16 Auto TP MDIX function................................................................................3-11
3.17
3.18
3.19
3.20
Port Locking...............................................................................................3-12
VLAN setting & Tag/Untag & port-base VLAN ......................................3-12
Priority Setting...........................................................................................3-13
LED Display ..............................................................................................3-13
Chapter 4 Register Description ....................................................................................4-1
4.1
4.2
4.3
EEPROM Content............................................................................................4-1
EEPROM Register Map...................................................................................4-1
EEPROM Register...........................................................................................4-2
Signature Register, offset: 0x00h..............................................................4-2
Configuration Registers, offset: 0x01h ~ 0x09h ......................................4-3
Reserved Register, offset: 0x0ah..............................................................4-3
Configuration Register, offset: 0x0bh......................................................4-4
Reserved Register, offset: 0x0ch~0x0dh..................................................4-4
VLAN priority Map Register, offset: 0x0eh .............................................4-4
TOS priority Map Register, offset: 0x0fh.................................................4-4
Packet with Priority: Normal packet content ..........................................4-5
VLAN Packet............................................................................................4-5
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18
4.3.19
4.3.20
TOS IP Packet..........................................................................................4-1
Miscellaneous Configuration Register, offset: 0x10h..............................4-1
VLAN mode select Register, offset: 0x11h...............................................4-2
Miscellaneous Configuration register, offset: 0x12h ..............................4-5
VLAN mapping table registers, offset: 0x22h ~ 0x13h............................4-5
Reserved Register, offset: 0x27h ~ 0x23h................................................4-5
Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset: 0x28h.............4-1
Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset: 0x29h.............4-1
Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah...............4-1
Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh...............4-1
Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register..4-1
ADM6996L
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