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ADM3061EBRZ-R7 PDF预览

ADM3061EBRZ-R7

更新时间: 2024-01-27 20:36:38
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亚德诺 - ADI /
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描述
IEC ESD Protected, 500 kbps/50 Mbps RS-485 Transceivers

ADM3061EBRZ-R7 数据手册

 浏览型号ADM3061EBRZ-R7的Datasheet PDF文件第5页浏览型号ADM3061EBRZ-R7的Datasheet PDF文件第6页浏览型号ADM3061EBRZ-R7的Datasheet PDF文件第7页浏览型号ADM3061EBRZ-R7的Datasheet PDF文件第9页浏览型号ADM3061EBRZ-R7的Datasheet PDF文件第10页浏览型号ADM3061EBRZ-R7的Datasheet PDF文件第11页 
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet  
ADM3065E/ADM3066E/ADM3067E/ADM3068E  
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All  
typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.  
Table 4.  
Parameter  
Symbol  
Min Typ Max Unit  
Test Conditions/Comments  
DRIVER  
Maximum Data Rate1  
Propagation Delay  
50  
Mbps  
ns  
tDPLH, tDPHL  
tDSKEW  
9
1
4
15  
2
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and  
Figure 40  
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and  
Figure 40  
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and  
Figure 40  
Skew  
ns  
ns  
Rise/Fall Times  
tDR, tDF  
6.7  
Enable to Output High  
Enable to Output Low  
Disable Time from Low  
Disable Time from High  
Enable Time from Shutdown to High  
Enable Time from Shutdown to Low  
RECEIVER  
tDZH  
tDZL  
tDLZ  
tDHZ  
tDZH(SHDN)  
tDZL(SHDN)  
10  
10  
10  
10  
30  
30  
30  
30  
ns  
ns  
ns  
ns  
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41  
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41  
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41  
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41  
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41  
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41  
2
550 2000 ns  
550 2000 ns  
2
Maximum Data Rate  
Propagation Delay  
50  
Mbps  
ns  
tRPLH, tRPHL  
tRSKEW  
tRZH  
20  
1
35  
3
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and  
Figure 42  
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and  
Figure 42  
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,  
see Figure 8 and Figure 44  
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,  
see Figure 8 and Figure 44  
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and  
Figure 44  
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and  
Figure 44  
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and  
Figure 43  
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and  
Figure 43  
Skew/Pulse Width Distortion  
Enable to Output High  
ns  
ns  
ns  
ns  
ns  
10  
10  
10  
10  
35  
35  
35  
35  
Enable to Output Low  
tRZL  
Disable Time from Low  
tRLZ  
Disable Time from High  
Enable from Shutdown to High  
Enable from Shutdown to Low  
TIME TO SHUTDOWN  
tRHZ  
3
tRZH(SHDN)  
450 2000 ns  
450 2000 ns  
ns  
3
tRZL(SHDN)  
4
tSHDN  
40  
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1.  
2
RE  
tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. = VCC for this condition.  
3
4
RE  
tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when changes from VCC to 0 V. DE = 0 V for this condition.  
Minimum time required to put the device into shutdown: DE and must be disabled for more than 40 ns for the device to go into shutdown.  
RE  
Rev. F | Page 8 of 28  
 

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