Dual Channel, High IP3,
100 MHz to 6 GHz Active Mixer
ADL5802
FE ATURES
FUNCTIONAL BLOCK DIAGRAM
VPOS RF1+ RF1– GND RF2+RF2–
Power conversion gain of 1.6 dB
Wideband RF, LO, and IF ports
SSB noise figure of 11 dB
24
23
22
21
20
19
1
2
3
4
18
17
16
15
GND
GND
GND
GND
OP2+
OP2–
Input IP3 of 28 dBm
Input P1dB of 12 dBm
Typical LO drive of 0 dBm
Low LO leakage
Single supply operation: 5 V @ 240 mA
Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
OP1+
OP1–
GND
5
6
14 GND
IP3
BIAS
ADL5802
APPLICATIONS
VPOS
13 VPOS
Cellular base station receivers
Main and diversity receiver designs
Radio link downconverters
7
8
9
10
11
12
LOIN GND VSET
ENBL GND LOIP
Figure 1.
GENERAL DESCRIPTION
The IF outputs are designed for a 200 Ω source impedance and
provide a typical voltage conversion gain of 7.6 dB when loaded
into a 200 Ω load.
The ADL5802 uses high linearity, double-balanced, active mixer
cores with integrated LO buffer amplifiers to provide high
dynamic range frequency conversion from 100 MHz to 6 GHz.
The mixers benefit from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. The high input linearity allows the device to be used
in demanding cellular applications where in-band blocking
signals may otherwise result in degradation in dynamic perform-
ance. The balanced active mixer arrangement provides superb
LO to RF and LO to IF leakage, typically better than −30 dBm.
The ADL5802 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm × 4 mm,
24-lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
Rev. 0
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