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ADL5372ACPZ-WP1 PDF预览

ADL5372ACPZ-WP1

更新时间: 2022-04-25 08:56:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 809K
描述
1500 MHz to 2500 MHz Quadrature Modulator

ADL5372ACPZ-WP1 数据手册

 浏览型号ADL5372ACPZ-WP1的Datasheet PDF文件第3页浏览型号ADL5372ACPZ-WP1的Datasheet PDF文件第4页浏览型号ADL5372ACPZ-WP1的Datasheet PDF文件第5页浏览型号ADL5372ACPZ-WP1的Datasheet PDF文件第7页浏览型号ADL5372ACPZ-WP1的Datasheet PDF文件第8页浏览型号ADL5372ACPZ-WP1的Datasheet PDF文件第9页 
ADL5372  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
COM1 1  
COM1 2  
VPS1 3  
VPS1 4  
VPS1 5  
VPS1 6  
18 VPS5  
17 VPS4  
16 VPS3  
15 VPS2  
14 VPS2  
13 VOUT  
F-MOD  
TOP VIEW  
(Not to Scale)  
Figure 2. Pin Configuration  
Table 3. Pin Function Descriptions  
Pin No. Mnemonic  
Description  
1, 2, 7, 10 to 12, COM1 to COM4  
21, 22  
Input Common Pins. Connect to ground plane via a low impedance path.  
3 to 6, 14 to 18 VPS1 to VPS5  
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure  
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.  
Adjacent power supply pins of the same name can share one capacitor (see Figure 25).  
8, 9  
LOIP, LOIN  
VOUT  
50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.  
AC-couple LOIN to ground and drive LO through LOIP.  
Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output  
is ground referenced.  
13  
19, 20, 23, 24  
IBBP, IBBN, QBBN, QBBP Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs  
must be dc-biased to 500 mV dc and must be driven from a low impedance source.  
Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential  
drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be  
externally biased.  
Exposed Paddle  
Connect to ground plane via a low impedance path.  
Rev. 0 | Page 6 of 24  
 

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