Datasheet > 信号电路 > 锁相环或频率合成电路> ADF4219LBRU-REEL

ADF4219LBRU-REEL

更新时间： 2024-02-01 10:49:13

品牌	Logo	应用领域
亚德诺 - ADI		信号电路锁相环或频率合成电路
页数	文件大小	规格书
24页	273K
描述
IC PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO20, MO-153AC, TSSOP-20, PLL or Frequency Synthesis Circuit

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技术参数
数据手册

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ADF4219LBRU-REEL 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	MO-153AC, TSSOP-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	5A991.B	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	ALSO REQUIRES A 3V TO 5.5V SUPPLY
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	6.5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	电源：	3/5,3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.6 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
Base Number Matches：	1

ADF4219LBRU-REEL 数据手册

ADF4217L/ADF4218L/ADF4219L

PIN FUNCTION DESCRIPTIONS

Mnemonic

_DD1

Function

Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as

close as possible to this pin. V_DD1 should have a value of between 2.6 V and 3.3 V. V_DD1 must have the same

potential as V_DD2.

V_P1

Power Supply for the RF Charge Pump. This should be greater than or equal to V_DD.

CP_RF

Output from the RF Charge Pump. When enabled, this provides I_CPto the external loop filter, which in turn

drives the external VCO.

DGND_RF

RF_INA

Ground Pin for the RF Digital Circuitry

Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.

RF_INB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF.

AGND_RF

REF_IN

Ground Pin for the RF Analog Circuitry

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input resistance of

100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.

DGND_IF

Ground Pin for the IF Digital, Interface, and Control Circuitry

MUXOUT

This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to

be accessed externally (Table V).

CLK

DATA

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches; the latch is selected using the control bits.

AGND_IF

Ground Pin for the IF Analog Circuitry

This pin is not connected internally (ADF4219L only).

IF_INB

Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF (ADF4217L/ADF4218L only).

IF_INA

DGND_IF

CP_IF

Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.

Ground Pin for the IF Digital, Interface, and Control Circuitry

Output from the IF Charge Pump. When enabled, this provides I_CPto the external loop filter, which in turn drives

the external VCO.

V_P2

Power Supply for the IF Charge Pump. This should be greater than or equal to V_DD.

_DD2

Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. V_DD2 should have a value of between 2.6 V and 3.3 V.

V_DD2 must have the same potential as V_DD1.

–6–

REV. C

1...3 4 567 8 9...24

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与ADF4219LBRU-REEL相关器件

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