ADF4116/ADF4117/ADF4118
Parameter
B Version1
Y Version2 Unit
Test Conditions/Comments
POWER SUPPLIES
AVDD
DVDD
2.7 to 5.5
AVDD
2.7 to 5.5
AVDD
V min to V max
VP
AVDD to 6.0
AVDD to 6.0 V min to V max
AVDD ≤ VP ≤ 6.0 V
IDD (AIDD + DIDD)6
ADF4116
ADF4117
ADF4118
5.5
5.5
7.5
0.4
1
mA max
mA max
mA max
mA max
μA typ
4.5 mA typical
4.5 mA typical
6.5 mA typical
TA = 25°C
7.5
0.4
1
IP
Low-Power Sleep Mode
NOISE CHARACTERISTICS
ADF4118 Normalized Phase Noise
−213
−213
dBc/Hz typ
Floor7
Phase Noise Performance8
ADF4116 540 MHz Output9
ADF4117 900 MHz Output10
ADF4118 900 MHz Output10
ADF4117 836 MHz Output11
ADF4118 1750 MHz Output12
ADF4118 1750 MHz Output13
ADF4118 1960 MHz Output14
Spurious Signals
@ VCO output
−89
−87
−90
−78
−85
−65
−84
−89
−87
−90
−78
−85
−65
−84
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 300 Hz offset and 30 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 Hz offset and 10 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
ADF4116 540 MHz Output10
ADF4117 900 MHz Output10
ADF4118 900 MHz Output10
ADF4117 836 MHz Output11
ADF4118 1750 MHz Output12
ADF4118 1750 MHz Output13
ADF4118 1960 MHz Output14
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 30 kHz/60 kHz and 30 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 10 kHz/20 kHz and 10 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
1 Operating temperature range for the B version is −40°C to +85°C.
2 Operating temperature range for the Y version is −40°C to +125°C.
3 This is the maximum operating frequency of the CMOS counters.
4 AC coupling ensures AVDD/2 bias. See Figure 35 for typical circuit.
5 Guaranteed by design.
6 TA = 25°C; AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz.
7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N
divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
8 The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer
(fREFOUT = 10 MHz @ 0 dBm).
9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop bandwidth = 20 kHz.
10
f
f
f
f
f
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop bandwidth = 20 kHz.
= 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop bandwidth = 3 kHz.
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop bandwidth = 20 kHz.
= 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop bandwidth = 1 kHz.
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop bandwidth = 20 kHz.
REFIN
REFIN
REFIN
REFIN
REFIN
11
12
13
14
Rev. D | Page 4 of 28