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ADF4108BRUZ-RL

更新时间： 2024-02-12 09:05:48
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 440K
描述
PLL Frequency Synthesizer

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ADF4108BRUZ-RL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01风险等级：5.7
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：4.4 mmBase Number Matches：1

ADF4108BRUZ-RL 数据手册

 浏览型号ADF4108BRUZ-RL的Datasheet PDF文件第4页浏览型号ADF4108BRUZ-RL的Datasheet PDF文件第5页浏览型号ADF4108BRUZ-RL的Datasheet PDF文件第6页浏览型号ADF4108BRUZ-RL的Datasheet PDF文件第8页浏览型号ADF4108BRUZ-RL的Datasheet PDF文件第9页浏览型号ADF4108BRUZ-RL的Datasheet PDF文件第10页 
ADF4108  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
V
R
P
SET  
DV  
CP  
DD  
MUXOUT  
LE  
CPGND  
AGND  
ADF4108  
PIN 1  
INDICATOR  
15 MUXOUT  
14 LE  
13 DATA  
12 CLK  
11 CE  
CPGND 1  
AGND 2  
AGND 3  
TOP VIEW 13  
(Not to Scale)  
12  
ADF4108  
TOP VIEW  
(Not to Scale)  
DATA  
CLK  
RF  
RF  
B
IN  
IN  
RF B 4  
IN  
11  
10  
9
A
RF A 5  
IN  
CE  
AV  
DD  
DGND  
REF  
IN  
NOTE: TRANSISTOR COUNT 6425 (CMOS),  
303 (BIPOLAR).  
Figure 3. TSSOP Pin Configuration for TSSOP  
Figure 4. LFCSP_VQ Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No.  
TSSOP LFCSP_VQ Mnemonic  
Description  
1
19  
RSET  
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.  
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is  
25.5  
RSET  
ICP MAX  
=
with RSET = 5.1 kΩ, ICP MAX = 5 mA.  
2
20  
CP  
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn  
drives the external VCO.  
3
4
5
1
2, 3  
4
CPGND  
AGND  
RFINB  
Charge Pump Ground. This is the ground return path for the charge pump.  
Analog Ground. This is the ground return path of the prescaler.  
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a  
small bypass capacitor, typically 100 pF. See Figure 12.  
6
7
5
6, 7  
RFINA  
AVDD  
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.  
Analog Power Supply. This voltage may range from 3.2 V to 3.6 V. Decoupling capacitors to the  
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value  
as DVDD.  
8
8
REFIN  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input  
resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or  
it can be ac-coupled.  
9
10  
9, 10  
11  
DGND  
CE  
Digital Ground.  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into  
three-state mode. Taking the pin high will power up the device, depending on the status of the  
power-down bit, F2.  
11  
12  
CLK  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is  
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS  
input.  
12  
13  
14  
15  
16  
13  
DATA  
LE  
Serial Data Input. The serial data is loaded MSB first with the 2 LSBs being the control bits. This input  
is a high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into  
one of the four latches, the latch being selected using the control bits.  
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference  
frequency to be accessed externally.  
Digital Power Supply. This may range from 3.2 V to 3.6 V. Decoupling capacitors to the digital ground  
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.  
14  
15  
MUXOUT  
DVDD  
VP  
16, 17  
18  
Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where  
VDD is 3.3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.  
Rev. 0 | Page 7 of 20  
 
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