Datasheet > ADD8608A8A-75B

ADD8608A8A-75B

更新时间： 2022-12-11 21:15:29

品牌	Logo	应用领域
威刚科技 - ADATA		动态存储器双倍数据速率
页数	文件大小	规格书
9页	508K
描述
Double Data Rate SDRAM

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数据手册

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ADD8608A8A-75B 数据手册

A-Data

ADD8608A8A

AC Characteristics

-75BA

-75B

Parameter

Symbol

tCK2.5

Unit

Min

7.5

Max

Min

7.5

Max

System clock

Cycle time

/CAS Latency = 2.5

/CAS Latency = 2

tCK2

Clock high pulse width

tCHW

tCLW

tAC

0.45

-0.75

0.75

0.55

0.45

0.55

CLK

Clock low pulse width

0.55

Access time form CK to /CK

Data strobe edge to clock edge

0.75

-0.75

0.75

tDQSCK

0.75

Clock to first rising edge of DQS delay tDQSS

1.25

CLK

/RAS cycle time

tRC

/RAS to /CAS delay

tRCD

tRAS

tRP

/RAS active time

120K

/RAS precharge time

/RAS to /RAS bank active delay

/CAS to /CAS delay

tRRD

tCCD

tDS

CLK

Data-in setup time (to DQS)

Data-in hold time (to DQS)

0.5

0.2

0.9

0.35

0.5

0.2

0.9

0.35

tDH

DQS Falling Edge to CLK Setup Time tDSS

DQS Falling Edge Hold Time from CLK tDSH

CLK

Input setup time

tIS

Input hold time

tIH

DQS-in high level width

DQS-in low level width

tDSH

tDSL

CLK

Clock to DQS write preamble setup time tWPRES

Write preamble

tWPST

tDQSQ

tMRD

0.4

0.5

0.4

0.5

CLK

Data strobe edge to output data edge

Mode register set cycle time

DQS read preamble

tRPRE

0.9

1.1

0.9

1.1

CLK

Rev 2 April, 2002

1...4 5 678 9

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