ADD8504/ADD8505/ADD8506
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
INA1
INB1
INA2
INB2
INA3
INB3
INA4
INB4
INA5
1
2
3
4
5
6
7
8
9
24 VCC1
23 OUT1
22 OUT2
21 OUT3
20 VCC2
19 A/B
INA1
INB1
INA2
INB2
INA3
INB3
INA4
INB4
INA5
1
2
3
4
5
6
7
8
9
20 VCC1
19 OUT1
18 OUT2
17 OUT3
16 VCC2
15 A/B
18 GND
17 GND
16 OUT4
15 OUT5
14 OUT6
13 VCC3
14 GND
13 GND
12 OUT4
11 OUT5
INB5 10
INA6 11
INB6 12
INB5 10
Figure 5. Pin Configuration, ADD8505, 5-Channel Buffer
Figure 4. Pin Configuration, ADD8506, 6-Channel Buffer
INA1
1
2
3
4
5
6
7
8
16 OUT1
15 OUT2
14 VCC1
13 A/B
INB1
INA2
INB2
INA3
INB3
INA4
INB4
12 GND
11 GND
10 OUT3
9
OUT4
Figure 6. Pin Configuration, ADD8504, 4-Channel Buffer
Table 5. Pin Function Descriptions
ADD8506 ADD8505 ADD8504
Pin No.
Pin No.
Pin No.
Mnemonic Function Description
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
INA1
INB1
INA2
INB2
INA3
INB3
INA4
INB4
INA5
INB5
INA6
INB6
VCC3
OUT6
OUT5
OUT4
GND
A/B
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power In
Output
Output
Output
Ground
Input
Power In
Output
Output
Output
Power In
Channel 1 Buffer Input A.
Channel 1 Buffer Input B.
Channel 2 Buffer Input A.
Channel 2 Buffer Input B.
Channel 3 Buffer Input A.
Channel 3 Buffer Input B.
Channel 4 Buffer Input A.
Channel 4 Buffer Input B.
Channel 5 Buffer Input A.
Channel 5 Buffer Input B.
Channel 6 Buffer Input A.
Channel 6 Buffer Input B.
Power Supply Input. Short to VCC1 and VCC2. Typically connected to 5 V.
Channel 6 Buffer Output.
Channel 5 Buffer Output.
Channel 4 Buffer Output.
Ground.
9
9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
9
11, 12
13
N/A
10
10
11
12
13
14
15
16
17, 18
19
20
21
22
23
24
10
N/A
N/A
N/A
N/A
11
12
13, 14
15
16
17
18
19
20
Switch Control. Logic High selects Input A; Logic Low selects Input B.
Power Supply Input. Short to VCC1 and VCC3. Typically connected to 5 V.
Channel 3 Buffer Output.
Channel 2 Buffer Output.
Channel 1 Buffer Output.
VCC2
OUT3
OUT2
OUT1
VCC1
15
16
14
Power Supply Input. Short to VCC2 and VCC3. Typically connected to 5 V.
Rev. D | Page 5 of 12