Datasheet > ADA4961

ADA4961

更新时间： 2023-12-20 18:46:29

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	716K
描述
低失真3.2 GHz RF DGA

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ADA4961 数据手册

Data Sheet

ADA4961

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

18 DNC

GND

VIN

VIN–

GND

MODE

+ 2

VOUT+

16 VOUT–

15 DNC

ADA4961

TOP VIEW

(Not to Scale)

14 NC

LATCH

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT THE EXPOSED PAD TO GROUND.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

1, 4, 5

2, 3

Mnemonic

Description

GND

VIN+, VIN−

MODE

Power Supply Ground. Connect to system ground plane.

Differential Inputs.

Mode Select Pin for Gain Control. Low indicates serial peripheral interface (SPI), and high (up to 3.3 V)

indicates parallel interface.

SDIO

A4/CLK

A3/CS

A2/FA

Serial Data Input/Output Pin for SPI Gain Control.

Bit A4 for Parallel Gain Control/Serial Clock Pin for SPI Gain Control.

Bit A3 for Parallel Gain Control/Chip Select Pin for SPI Gain Control.

Bit A2 for Parallel Gain Control/Fast Attack Pin for SPI Gain Control.

Bit A1 for Parallel Gain Control.

Bit A0 for Parallel Gain Control.

Latch Input Asserts Parallel Gain Control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode.

Do Not Connect. Do not connect to this pin.

LATCH

14, 15, 18 DNC

16, 17

VOUT−, VOUT+ Differential Outputs.

PWUP

Power-Up Control Input Pin. A logic high (3.3 V) asserts power-up. A logic low asserts power-down.

Power/Performance Control Input Pin. A logic low indicates high power and high performance, and a logic

high indicates low power and nominal performance. Low power mode must be asserted with V_MIN= 2.8 V.

VCC1

VCC2

VCC3

VCC4

EPAD

Positive Power Supply. Connect to 5 V or 3.3 V.

Exposed Pad. Connect the exposed pad to ground.

Rev. C | Page 7 of 24

1...4 5 678 9 10...24

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