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AD9927

更新时间: 2024-02-18 20:58:31
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
100页 832K
描述
14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator

AD9927 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128针数:128
Reach Compliance Code:unknown风险等级:5.66
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-XBGA-B128
JESD-609代码:e1长度:9 mm
湿度敏感等级:3功能数量:1
端子数量:128最高工作温度:85 °C
最低工作温度:-25 °C封装主体材料:UNSPECIFIED
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.4 mm
最大供电电压 (Vsup):2 V最小供电电压 (Vsup):1.6 V
表面贴装:YES温度等级:OTHER
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:9 mm
Base Number Matches:1

AD9927 数据手册

 浏览型号AD9927的Datasheet PDF文件第4页浏览型号AD9927的Datasheet PDF文件第5页浏览型号AD9927的Datasheet PDF文件第6页浏览型号AD9927的Datasheet PDF文件第8页浏览型号AD9927的Datasheet PDF文件第9页浏览型号AD9927的Datasheet PDF文件第10页 
AD9927  
VERTICAL DRIVER SPECIFICATIONS  
VH1, VH2 = 15 V. VM1, VM2, VMM = 0 V. VL1, VL2, VLL = −7.5 V. CL shown in load model, 25°C.  
Table 5.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
V-DRIVER OUTPUTS (SIMPLIFIED LOAD CONDITIONS, 3000 pF to GROUND)  
Delay Time, VL to VM and VM to VH  
Delay Time, VM to VL and VH to VM  
Rise Time, VL to VM  
Rise Time, VM to VH  
Fall Time, VM to VL  
Fall Time, VH to VM  
Output Currents  
tPLM, tPMH  
tPML, tPHM  
tRLM  
tRMH  
tFML  
35  
35  
125  
260  
220  
125  
ns  
ns  
ns  
ns  
ns  
ns  
tFHM  
@ −7.25 V  
@ −0.25 V  
@ +0.25 V  
@ +14.75 V  
10  
−22  
22  
mA  
mA  
mA  
mA  
Ω
−10  
RON  
35  
SUBCK OUTPUT (SIMPLIFIED LOAD CONDITIONS, 1000 pF to GROUND)  
Delay Time, VLL to VH  
Delay Time, VH to VLL  
Delay Time, VLL to VMM  
Delay Time, VMM to VH  
Delay Time, VH to VMM  
Delay Time, VMM to VLL  
Rise Time, VLL to VH  
Rise Time, VLL to VMM  
Rise Time, VMM to VH  
Fall Time, VH to VLL  
Fall Time, VH to VMM  
Fall Time, VMM to VLL  
Output Currents  
tPLH  
tPHL  
tPLM  
tPMH  
tPHM  
tPML  
tRLH  
tRLM  
tRMH  
tFHL  
tFHM  
tFML  
25  
30  
25  
25  
30  
25  
40  
45  
30  
40  
90  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
@ −7.25 V  
@ −0.25 V  
@ +0.25 V  
@ +14.75 V  
20  
−12  
12  
mA  
mA  
mA  
mA  
Ω
−20  
RON  
35  
V-DRIVER  
50%  
50%  
INPUT  
tRLM, tRMH, tRLH  
tPML  
90%  
, tPHM, tPHL  
90%  
V-DRIVER  
OUTPUT  
tPLM  
,
tPMH, tPLH  
tFML, tFHM, tFHL  
10%  
10%  
Figure 2. Definition of V-Driver Timing Specifications  
Rev. 0 | Page 7 of 100  
 

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