Datasheet > AD9913BCPZ1

AD9913BCPZ1

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
32页	687K
描述
Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer

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AD9913BCPZ1 数据手册

AD9913

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V 5ꢀ, T = 25°C, R_SET= 4.64 kΩ, DAC full-scale current = 2 mA, external

reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.

Table 1.

Parameter

Conditions/Comments

Min

Typ

Max

Unit

REF_CLK INPUT CHARACTERISTICS

Frequency Range

REF_CLK Multiplier

Disabled

Enabled

Full temperature range

VCO1

250

MHz

μs

MHz

REF_CLK Input Divider Frequency

VCO Oscillation Frequency

100

VCO2

PLL Lock Time

External Crystal Mode

CMOS Mode

25 MHz reference clock, 10× PLL

VIH

VIL

0.9

0.65

Input Capacitance

Input Impedance (Differential)

Input Impedance (Single-Ended)

Duty Cycle

2.7

1.35

kΩ

REF_CLK Input Level

355

1000

mV p-p

DAC OUTPUT CHARACTERISTICS

Full-Scale Output Current

Gain Error

Output Offset

Differential Nonlinearity

Integral Nonlinearity

AC Voltage Compliance Range

SPURIOUS-FREE DYNAMIC RANGE

SERIAL PORT TIMING CHARACTERISTICS

SCLK Frequency

4.6

−6

+0.1

+0.4

+0.5

%FS

μA

LSB

−14

−0.4

−0.5

±400

Refer to Figure 6

MHz

SCLK Pulse Width

Low

High

17.5

3.5

SCLK Rise/Fall Time

Data Setup Time to SCLK

Data Hold Time to SCLK

Data Valid Time in Read Mode

PARALLEL PORT TIMING CHARACTERISTICS

PCLK Frequency

5.5

MHz

PCLK Pulse Width

Low

High

PCLK Rise/Fall Time

Address/Data Setup Time to PCLK

Address/Data Hold Time to PCLK

Data Valid Time in Read Mode

IO_UPDATE/PROFILE(2:0) TIMING

Setup Time to SYNC_CLK

3.0

0.3

0.5

Hold Time to SYNC_CLK

SYNC_CLK cycles

Rev. 0 | Page 3 of 32

1 234 5 6 7...32

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