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AD9888KSZ-140 PDF预览

AD9888KSZ-140

更新时间: 2024-02-16 06:20:19
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路
页数 文件大小 规格书
36页 501K
描述
100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface

AD9888KSZ-140 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:FQFP,针数:128
Reach Compliance Code:unknown风险等级:5.07
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PQFP-G128JESD-609代码:e3
长度:20 mm湿度敏感等级:3
功能数量:1端子数量:128
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:RECTANGULAR封装形式:FLATPACK, FINE PITCH
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:3.4 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

AD9888KSZ-140 数据手册

 浏览型号AD9888KSZ-140的Datasheet PDF文件第30页浏览型号AD9888KSZ-140的Datasheet PDF文件第31页浏览型号AD9888KSZ-140的Datasheet PDF文件第32页浏览型号AD9888KSZ-140的Datasheet PDF文件第34页浏览型号AD9888KSZ-140的Datasheet PDF文件第35页浏览型号AD9888KSZ-140的Datasheet PDF文件第36页 
Data Sheet  
AD9888  
HSYNC pulses are present. Because HSYNC pulses are relatively  
short in width, the counter only reaches a value of N before the  
pulse ends. It then starts counting down, eventually reaching 0  
before the next HSYNC pulse arrives. The specific value of N varies  
among video modes, but is always less than 255. For example, with  
a 1 μs width HSYNC, the counter reaches only 5 (1 μs/200 ns = 5).  
When VSYNC is present on the composite sync, the counter  
also counts up. However, because the VSYNC signal is much  
longer, the counter reaches a higher number, M. For most video  
modes, M is at least 255. Therefore, VSYNC can be detected on  
the composite sync signal by detecting when the counter counts  
to higher than N. The specific count that triggers detection (T)  
can be programmed through the serial register (Address 0x0F).  
SYNC SLICER  
The purpose of the sync slicer is to extract the sync signal from  
the green graphics channel. A sync signal is not present on all  
graphics signals, only those with sync-on-green. The sync signal  
is extracted from the green channel in a two-step process. First,  
the SOG input is clamped to its negative peak (typically 0.3 V  
below the black level). Next, the signal goes to a comparator  
with a variable trigger level, nominally 0.15 V above the clamped  
level. The “sliced” sync is typically a composite sync signal  
containing both HSYNC and VSYNC.  
SYNC SEPARATOR  
A sync separator extracts the VSYNC signal from a composite sync  
signal by using a low-pass filter-like or integrator-like operation.  
It works on the idea that the VSYNC signal stays active for a much  
longer time than the HSYNC signal. Therefore, the sync separator  
rejects any signal shorter than a threshold value, which is some-  
where between an HSYNC pulse width and a VSYNC pulse width.  
After VSYNC is detected, there is a similar process to detect when  
it becomes inactive. Upon detection, the counter first resets to 0,  
and then starts counting up when VSYNC disappears. Similar to  
the previous case, the sync separator detects the absence of VSYNC  
when the counter reaches the threshold count (T). In this way,  
the sync separator rejects noise and/or serration pulses. After  
VSYNC is detected to be absent, the counter resets to 0 and begins  
the cycle again.  
The sync separator on the AD9888 is an 8-bit digital counter  
with a 5 MHz clock. It works independently of the polarity of  
the composite sync signal. Polarities are determined elsewhere  
on the chip. The basic idea is that the counter counts up when  
Rev. C | Page 33 of 36  
 
 
 

AD9888KSZ-140 替代型号

型号 品牌 替代类型 描述 数据表
AD9888KS-140 ADI

完全替代

100/140/170/205 MSPS Analog Flat Panel Interface

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