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AD9844AJSTZ PDF预览

AD9844AJSTZ

更新时间: 2024-01-09 08:57:35
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 商用集成电路
页数 文件大小 规格书
17页 842K
描述
SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, LQFP-48

AD9844AJSTZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:48
Reach Compliance Code:unknown风险等级:5.11
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
湿度敏感等级:3功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:OTHER
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
Base Number Matches:1

AD9844AJSTZ 数据手册

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AD9844A  
chain at the specified gain setting. The output noise can be  
converted to an equivalent voltage, using the relationship 1 LSB  
= (ADC Full Scale/2N codes) when N is the bit resolution of the  
ADC. For the AD9844A, 1 LSB is 0.5 mV.  
DEFINITIONS OF SPECIFICATIONS  
DIFFERENTIAL NONLINEARITY (DNL)  
An ideal ADC exhibits code transitions that are exactly 1 LSB  
apart. DNL is the deviation from this ideal value. Thus every code  
must have a finite width. No missing codes guaranteed to 12-bit  
resolution indicates that all 4096 codes, respectively, must be  
present over all operating conditions.  
POWER SUPPLY REJECTION (PSR)  
The PSR is measured with a step change applied to the supply  
pins. This represents a very high-frequency disturbance on the  
AD9844A’s power supply. The PSR specification is calcu-  
lated from the change in the data outputs for a given step  
change in the supply voltage.  
PEAK NONLINEARITY  
Peak nonlinearity, a full signal chain specification, refers to the  
peak deviation of the output of the AD9844A from a true straight  
line. The point used as “zero scale” occurs 1/2 LSB before the  
first code transition. “Positive full scale” is defined as a Level  
1, 1/2 LSB beyond the last code transition. The deviation is mea-  
sured from the middle of each particular output code to the  
true straight line. The error is then expressed as a percentage of the  
2 V ADC full-scale signal. The input signal is always appropriately  
gained up to fill the ADC’s full-scale range.  
INTERNAL DELAY FOR SHP/SHD  
The internal delay (also called aperture delay) is the time delay  
that occurs from when a sampling edge is applied to the AD9844A  
until the actual sample of the input signal is held. Both SHP and  
SHD sample the input signal during the transition from low to  
high, so the internal delay is measured from each clock’s rising  
edge to the instant the actual internal sample is taken.  
TOTAL OUTPUT NOISE  
The rms output noise is measured using histogram techniques.  
The standard deviation of the ADC output codes is calculated  
in LSB, and represents the rms noise level of the total signal  
EQUIVALENT INPUT CIRCUITS  
DVDD  
ACVDD  
330  
ACVSS  
ACVSS  
DVSS  
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,  
CLPDM, HD, VD, PBLK, SCK, SL  
Figure 3. CCDIN (Pin 30)  
DVDD  
DRVDD  
DATA  
DVDD  
DVDD  
DATA IN  
330  
THREE-  
STATE  
DATA OUT  
DOUT  
RNW  
DVSS  
DVSS  
DVSS  
Figure 4. SDATA (Pin 47)  
DVSS  
DRVSS  
Figure 2. Data Outputs  
REV. 0  
–7–  

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