5秒后页面跳转
捷配首页

Datasheet > AD9760AR
AD9760AR PDF预览

AD9760AR

更新时间： 2024-01-26 06:31:00
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
23页 412K
描述
10-Bit, 125 MSPS TxDAC D/A Converter

阅读下载

获取价格

AD9760AR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：28
Reach Compliance Code：unknown风险等级：5.28
最大模拟输出电压：1.25 V最小模拟输出电压：-1 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：PARALLEL, WORDJESD-30 代码：R-PDSO-G28
JESD-609代码：e3长度：17.9 mm
最大线性误差 (EL)：0.0977%湿度敏感等级：1
位数：10功能数量：1
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：2.65 mm
标称安定时间 (tstl)：0.035 µs标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.5 mmBase Number Matches：1

AD9760AR 数据手册

 浏览型号AD9760AR的Datasheet PDF文件第3页浏览型号AD9760AR的Datasheet PDF文件第4页浏览型号AD9760AR的Datasheet PDF文件第5页浏览型号AD9760AR的Datasheet PDF文件第7页浏览型号AD9760AR的Datasheet PDF文件第8页浏览型号AD9760AR的Datasheet PDF文件第9页 
AD9760  
DEFINITIONS OF SPECIFICATIONS  
Temperature Drift  
Linearity Error (Also Called Integral Nonlinearity or INL)  
Linearity error is defined as the maximum deviation of the  
actual analog output from the ideal output, determined by a  
straight line drawn from zero to full scale.  
Temperature drift is specified as the maximum change from the  
ambient (+25°C) value to the value at either TMIN or TMAX. For  
offset and gain drift, the drift is reported in ppm of full-scale  
range (FSR) per degree C. For reference drift, the drift is  
reported in ppm per degree C.  
Differential Nonlinearity (or DNL)  
DNL is the measure of the variation in analog value, normalized  
to full scale, associated with a 1 LSB change in digital input  
code.  
Power Supply Rejection  
The maximum change in the full-scale output as the supplies  
are varied from nominal to minimum and maximum specified  
voltages.  
Monotonicity  
A D/A converter is monotonic if the output either increases or  
remains constant as the digital input increases.  
Settling Time  
The time required for the output to reach and remain within a  
specified error band about its final value, measured from the  
start of the output transition.  
Offset Error  
The deviation of the output current from the ideal of zero is  
called offset error. For IOUTA, 0 mA output is expected when the  
inputs are all 0s. For IOUTB, 0 mA output is expected when all  
inputs are set to 1s.  
Glitch Impulse  
Asymmetrical switching times in a DAC give rise to undesired  
output transients that are quantified by a glitch impulse. It is  
specified as the net area of the glitch in pV-s.  
Gain Error  
The difference between the actual and ideal output span. The  
actual span is determined by the output when all inputs are set  
to 1s minus the output when all inputs are set to 0s.  
Spurious-Free Dynamic Range  
The difference, in dB, between the rms amplitude of the output  
signal and the peak spurious signal over the specified bandwidth.  
Output Compliance Range  
Total Harmonic Distortion  
The range of allowable voltage at the output of a current-output  
DAC. Operation beyond the maximum compliance limits may  
cause either output stage saturation or breakdown resulting in  
nonlinear performance.  
THD is the ratio of the rms sum of the first six harmonic  
components to the rms value of the measured output signal. It is  
expressed as a percentage or in decibels (dB).  
+5V  
0.1␮F  
REFLO  
+1.20V REF  
REFIO  
COMP1  
AVDD  
ACOM  
AD9760  
50pF  
0.1␮F  
PMOS  
0.1␮F  
COMP2  
CURRENT SOURCE  
ARRAY  
FS ADJ  
MINI-CIRCUITS  
T1-1T  
R
2k⍀  
SET  
TO HP3589A  
SPECTRUM/  
NETWORK  
ANALYZER  
50⍀ INPUT  
+5V  
DVDD  
I
OUTA  
LSB  
SWITCHES  
SEGMENTED SWITCHES  
100⍀  
DCOM  
I
OUTB  
FOR DB11–DB3  
CLOCK  
SLEEP  
LATCHES  
DVDD  
DCOM  
50⍀  
50⍀  
20pF  
50⍀  
RETIMED  
20pF  
CLOCK  
DIGITAL  
DATA  
OUTPUT*  
CLOCK  
OUTPUT  
* AWG2021 CLOCK RETIMED  
SUCH THAT DIGITAL DATA  
TRANSITIONS ON FALLING EDGE  
OF 50% DUTY CYCLE CLOCK.  
LECROY 9210  
PULSE GENERATOR  
TEKTRONIX  
AWG-2021  
Figure 2. Basic AC Characterization Test Setup  
REV. B  
–6–  
1...3456789...23

下载PDF

与AD9760AR相关器件

型号 品牌 描述 获取价格 数据表
AD9760AR50 ADI 10-Bit, 125 MSPS TxDAC D/A Converter

获取价格
AD9760AR50 ROCHESTER PARALLEL, WORD INPUT LOADING, 0.035us SETTLING TIME, 10-BIT DAC, PDSO28, 0.300 INCH, SOIC-

获取价格
AD9760AR50RL ROCHESTER PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28, 0.300 INCH, SOIC

获取价格
AD9760ARRL ADI 10-Bit, 125 MSPS TxDAC® D/A Converter

获取价格
AD9760ARRL ROCHESTER PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28, 0.300 INCH, SOIC

获取价格
AD9760ARU ADI 10-Bit, 125 MSPS TxDAC D/A Converter

获取价格

与AD9760AR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证