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AD9755ASTRL

更新时间： 2024-02-25 00:58:49
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
28页 532K
描述
14-Bit, 300 MSPS High Speed TxDAC+ D/A Converter

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AD9755ASTRL 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP48,.35SQ,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.34
Is Samacsys：N最大模拟输出电压：1.25 V
最小模拟输出电压：-1 V转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：PARALLEL, WORD
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm最大线性误差 (EL)：0.0305%
湿度敏感等级：3模拟输入通道数量：1
位数：14功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP48,.35SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
标称安定时间 (tstl)：0.011 µs子类别：Analog to Digital Converters
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm
Base Number Matches：1

AD9755ASTRL 数据手册

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AD9755  
TERMINOLOGY  
Power Supply Rejection  
Linearity Error (Also Called Integral Nonlinearity or INL)  
Linearity error is defined as the maximum deviation of the actual  
analog output from the ideal output, determined by a straight  
line drawn from zero to full scale.  
The maximum change in the full-scale output as the supplies  
are varied from minimum to maximum specified voltages.  
Settling Time  
The time required for the output to reach and remain within a  
specified error band around its final value, measured from the  
start of the output transition.  
Differential Nonlinearity (DNL)  
DNL is the measure of the variation in analog value, normalized  
to full scale, associated with a 1 LSB change in digital input code.  
Glitch Impulse  
Monotonicity  
Asymmetrical switching times in a DAC cause undesired output  
transients that are quantified by a glitch impulse. It is specified  
as the net area of the glitch in pV-s.  
A D/A converter is monotonic if the output either increases or  
remains constant as the digital input increases.  
Offset Error  
Spurious-Free Dynamic Range  
The deviation of the output current from the ideal of zero is  
called offset error. For IOUTA, 0 mA output is expected when the  
inputs are all 0s. For IOUTB, 0 mA output is expected when the  
inputs are all 1s.  
The difference, in dB, between the rms amplitude of the output  
signal and the peak spurious signal over the specified bandwidth.  
Total Harmonic Distortion (THD)  
THD is the ratio of the rms sum of the first six harmonic com-  
ponents to the rms value of the measured fundamental. It is  
expressed as a percentage or in decibels (dB).  
Gain Error  
The difference between the actual and ideal output span. The  
actual span is determined by the output when all inputs are set  
to 1s, minus the output when all inputs are set to 0s.  
Signal-to-Noise Ratio (SNR)  
SNR is the ratio of the rms value of the measured output signal  
to the rms sum of all other spectral components below the  
Nyquist frequency, excluding the first six harmonics and dc.  
The value for SNR is expressed in decibels.  
Output Compliance Range  
The range of allowable voltage at the output of a current-output  
DAC. Operation beyond the maximum compliance limits may  
cause either output stage saturation or breakdown, resulting in  
nonlinear performance.  
Adjacent Channel Power Ratio (ACPR)  
A ratio in dBc between the measured power within a channel  
relative to its adjacent channel.  
Temperature Drift  
Specified as the maximum change from the ambient (25°C) value  
to the value at either TMIN or TMAX. For offset and gain drift, the  
drift is reported in ppm of full-scale range (FSR) per degree C.  
For reference drift, the drift is reported in ppm per degree C.  
3.0V TO 3.6V  
MINI  
CIRCUITS  
T1-1T  
TO ROHDE &  
SCHWARZ  
FSEA30  
SPECTRUM  
ANALYZER  
AVDD  
DVDD  
I
OUTA  
SEGMENTED  
SWITCHES FOR  
DB0 TO DB13  
1.2V REF  
REFIO  
PMOS CURRENT  
SOURCE ARRAY  
DAC  
I
OUTB  
50⍀  
50⍀  
PLLVDD  
CLKVDD  
RESET  
LPF  
CLKCOM  
DIV0  
FSADJ  
0.1␮F  
DAC LATCH  
2–1 MUX  
R
SET  
2k⍀  
PLL  
CIRCUITRY  
AD9755  
DCOM  
DIV1  
PORT 1 LATCH  
PORT 2 LATCH  
DB0–DB13  
ACOM  
CLK+  
PLLLOCK  
1k⍀  
CLK–  
DB0–DB13  
DIGITAL DATA INPUTS  
3.0V TO 3.6V  
MINI  
CIRCUITS  
T1-1T  
TEKTRONIX DG2020  
OR  
AWG2021 w/OPTION 4  
1k⍀  
HP8644  
SIGNAL  
GENERATOR  
PLL ENABLED  
PLL DISABLED  
LECROY 9210  
PULSE GENERATOR  
(FOR DATA RETIMING)  
Figure 2. Basic AC Characterization Test Setup  
REV. B  
–7–  
1...45678910...28

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