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AD9613BCPZ-170 PDF预览

AD9613BCPZ-170

更新时间: 2024-02-18 08:40:02
品牌 Logo 应用领域
亚德诺 - ADI 转换器模数转换器
页数 文件大小 规格书
36页 1074K
描述
12-Bit, 170 MSPS/210 MSPS/250 MSPS,1.8 V Dual Analog-to-Digital Converter (ADC)

AD9613BCPZ-170 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC64,.35SQ,20针数:64
Reach Compliance Code:compliantECCN代码:3A991.C.2
HTS代码:8542.39.00.01风险等级:1.74
最大模拟输入电压:1.75 V最小模拟输入电压:
最长转换时间:0.0058 µs转换器类型:ADC, FLASH METHOD
JESD-30 代码:S-XQCC-N64JESD-609代码:e3
长度:9 mm最大线性误差 (EL):0.0122%
湿度敏感等级:3模拟输入通道数量:2
位数:12功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE
输出格式:PARALLEL, WORD封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC64,.35SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225电源:1.8 V
认证状态:Not Qualified采样速率:170 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:1 mm
子类别:Analog to Digital Converters标称供电电压:1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:9 mm
Base Number Matches:1

AD9613BCPZ-170 数据手册

 浏览型号AD9613BCPZ-170的Datasheet PDF文件第2页浏览型号AD9613BCPZ-170的Datasheet PDF文件第3页浏览型号AD9613BCPZ-170的Datasheet PDF文件第4页浏览型号AD9613BCPZ-170的Datasheet PDF文件第5页浏览型号AD9613BCPZ-170的Datasheet PDF文件第6页浏览型号AD9613BCPZ-170的Datasheet PDF文件第7页 
12-Bit, 170 MSPS/210 MSPS/250 MSPS,  
1.8 V Dual Analog-to-Digital Converter (ADC)  
AD9613  
Data Sheet  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
AGND  
DRVDD  
SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS  
SFDR = 86 dBc at 185 MHz fIN and 250 MSPS  
−149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and  
250 MSPS  
Total power consumption: 770 mW at 250 MSPS  
1.8 V supply voltages  
VIN+A  
PIPELINE  
12-BIT  
ADC  
12  
D0±  
.
.
.
.
.
VIN–A  
VCM  
PARALLEL  
DDR LVDS  
AND  
AD9613  
VIN+B  
PIPELINE  
12-BIT  
ADC  
12  
D11±  
DRIVERS  
LVDS (ANSI-644 levels) outputs  
VIN–B  
Integer 1-to-8 input clock divider (625 MHz maximum input)  
Sample rates of up to 250 MSPS  
IF sampling frequencies of up to 400 MHz  
Internal ADC voltage reference  
Flexible analog input range  
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)  
ADC clock duty cycle stabilizer  
DCO±  
OR±  
REFERENCE  
1 TO 8  
CLOCK  
DIVIDER  
SERIAL PORT  
OEB  
PDWN  
SCLK SDIO  
CSB  
CLK+  
CLK– SYNC  
95 dB channel isolation/crosstalk  
Serial port control  
NOTES  
1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A  
AND CHANNEL B LVDS OUTPUT DATA.  
Energy-saving power-down modes  
Figure 1.  
APPLICATIONS  
Communications  
Diversity radio systems  
Multimode digital receivers (3G)  
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE  
I/Q demodulation systems  
Smart antenna systems  
General-purpose software radios  
Ultrasound equipment  
Broadband data applications  
GENERAL DESCRIPTION  
The AD9613 is a dual 12-bit, analog-to-digital converter (ADC)  
with sampling speeds of up to 250 MSPS. The AD9613 is designed  
to support communications applications where low cost, small  
size, wide bandwidth, and versatility are desired.  
Programming for setup and control is accomplished using a  
3-wire SPI-compatible serial interface.  
The AD9613 is available in a 64-lead LFCSP and is specified  
over the industrial temperature range of −40°C to +85°C. This  
product is protected by a U.S. patent.  
The dual ADC cores feature a multistage, differential pipelined  
architecture with integrated output error correction logic. Each  
ADC features wide bandwidth inputs supporting a variety of user-  
selectable input ranges. An integrated voltage reference eases design  
considerations. A duty cycle stabilizer (DCS) is provided to  
compensate for variations in the ADC clock duty cycle,  
PRODUCT HIGHLIGHTS  
1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.  
2. Fast overrange and threshold detect.  
3. Proprietary differential input maintains excellent SNR  
performance for input frequencies of up to 400 MHz.  
4. SYNC input allows synchronization of multiple devices.  
5. 3-pin, 1.8 V SPI port for register programming and register  
readback.  
allowing the converters to maintain excellent performance.  
The ADC output data is routed directly to the two external 12-bit  
LVDS output ports and formatted as either interleaved or channel  
multiplexed.  
6. Pin compatibility with the AD9643, allowing a simple  
migration up to 14 bits, and with the AD6649 and the AD6643.  
Flexible power-down options allow significant power savings,  
when desired.  
Rev. C  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  

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