AD9520-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Mode 1: Clock Distribution or External
VCO <1600 MHz ................................................................... 30
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 7
Clock Outputs............................................................................... 7
Timing Characteristics ................................................................ 8
Timing Diagrams ..................................................................... 9
Mode 2: High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz .................................................. 32
Phase-Locked Loop (PLL) .................................................... 34
Configuration of the PLL...................................................... 34
Phase Frequency Detector (PFD) ........................................ 34
Charge Pump (CP)................................................................. 35
On-Chip VCO ........................................................................ 35
PLL External Loop Filter....................................................... 35
PLL Reference Inputs............................................................. 35
Reference Switchover............................................................. 36
Reference Divider R............................................................... 36
VCXO/VCO Feedback Divider N: P, A, B, R ..................... 36
Digital Lock Detect (DLD) ................................................... 38
Analog Lock Detect (ALD)................................................... 38
Current Source Digital Lock Detect (CSDLD) .................. 38
Clock Output Additive Phase Noise (Distribution Only; VCO
Divider Not Used) ...................................................................... 10
Clock Output Absolute Phase Noise (Internal VCO Used).. 11
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO)............................................................................. 11
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO)............................................................................. 11
CLK
)................ 39
External VCXO/VCO Clock Input (CLK/
Holdover.................................................................................. 39
Manual Holdover Mode........................................................ 39
Automatic/Internal Holdover Mode.................................... 39
Frequency Status Monitors ................................................... 41
VCO Calibration .................................................................... 42
Zero Delay Operation................................................................ 43
Internal Zero Delay Mode..................................................... 43
External Zero Delay Mode.................................................... 43
Clock Distribution ..................................................................... 44
Operation Modes ................................................................... 44
CLK or VCO Direct-to-LVPECL Outputs.......................... 44
Clock Frequency Division..................................................... 45
VCO Divider........................................................................... 45
Channel Dividers ................................................................... 45
Synchronizing the Outputs—SYNC Function................... 47
LVPECL Output Drivers ....................................................... 48
CMOS Output Drivers .......................................................... 49
Reset Modes ................................................................................ 49
Power-On Reset...................................................................... 49
Clock Output Absolute Time Jitter (Clock Generation Using
External VCXO) ......................................................................... 12
Clock Output Additive Time Jitter (VCO Divider Not Used)
....................................................................................................... 12
Clock Output Additive Time Jitter (VCO Divider Used) ..... 13
Serial Control Port—SPI Mode ................................................ 13
Serial Control Port—IꢀC Mode ................................................ 14
,
, and
Pins ..................................................... 15
RESET
PD SYNC
Serial Port Setup Pins: SP1, SP0 ............................................... 15
LD, STATUS, REFMON Pins.................................................... 15
Power Dissipation....................................................................... 16
Absolute Maximum Ratings.......................................................... 17
Thermal Resistance .................................................................... 17
ESD Caution................................................................................ 17
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 26
Detailed Block Diagram ................................................................ 27
Theory of Operation ...................................................................... 28
Operational Configurations...................................................... 28
Mode 0: Internal VCO and Clock Distribution ................. 28
RESET
Hardware Reset via the
Pin ..................................... 49
Soft Reset via the Serial Port................................................. 49
Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via
the Serial Port ......................................................................... 49
Rev. 0 | Page 2 of 84
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