AD8328
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage
PIN CONFIGURATIONS
20-Lead
20-Lead
QSOP
LFCSP
VIN+, VIN– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V p-p
DATEN, SDATA, CLK,
SLEEP, TXEN . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
1
2
GND
20
19
18
17
16
15
14
13
12
GND
V
V
CC
CC
20 19 18 17 16
3
Internal Power Dissipation
GND
GND
TXEN
RAMP
V
1
2
3
15
14
13
RAMP
V
GND
GND
4
QSOP, LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD8328
OUT
+
5
V
OUT
+
IN+
AD8328
TOP VIEW
V
V
(Not to Scale)
TOP VIEW
6
OUT–
V
IN+
V
IN–
OUT
–
(Not to Scale)
V
4
5
12 BYP
11
7
GND
DATEN
SDATA
CLK
IN–
BYP
NC
NC
GND
8
9
SLEEP
6
7
8
9
10
10
11 GND
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. Pin No.
20-Lead 20-Lead
LFCSP QSOP
Mnemonic
Description
Common External Ground Reference
1 ,2, 5,
1, 3, 4, 7,
GND
9, 18, 19 11, 20
17, 20
2, 19
VCC
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
3
4
6
5
6
8
VIN+
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously
inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous
gain state) and simultaneously enables the register for serial data load.
VIN–
DATEN
7
8
9
SDATA
CLK
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
10
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data-word to be valid at or before this clock transition.
10
12
SLEEP
Low Power Sleep Mode. In the Sleep mode, the AD8328’s supply current is reduced to 20 µA. A Logic 0
powers down the part (High ZOUT State), and a Logic 1 powers up the part.
12
13
14
15
16
14
15
16
17
18
BYP
Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).
Negative Output Signal
VOUT–
VOUT+
RAMP
TXEN
Positive Output Signal
External RAMP Capacitor (optional)
Logic 0 disables forward transmission. Logic 1 enables forward transmission.
ORDERING GUIDE
Model
Temperature Range
Package Description
θJA
Package Option
AD8328ARQ
–40°C to +85°C
–40°C to +85°C
20-Lead QSOP
20-Lead QSOP
Evaluation Board
20-Lead LFCSP
20-Lead LFCSP
Evaluation Board
83.2°C/W1
RQ-20
RQ-20
AD8328ARQ-REEL
AD8328ARQ-EVAL
AD8328ACP
AD8328ACP-REEL
AD8328ACP-EVAL
83.2°C/W1
–40°C to +85°C
–40°C to +85°C
30.4°C/W2
30.4°C/W2
CP-20
CP-20
1Thermal Resistance measured on SEMI standard 4-layer board.
2Thermal Resistance measured on SEMI standard 4-layer board, paddle soldered to board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8328 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
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