5秒后页面跳转
AD8315_06 PDF预览

AD8315_06

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 控制器GSM
页数 文件大小 规格书
24页 561K
描述
50 dB GSM PA Controller

AD8315_06 数据手册

 浏览型号AD8315_06的Datasheet PDF文件第1页浏览型号AD8315_06的Datasheet PDF文件第2页浏览型号AD8315_06的Datasheet PDF文件第4页浏览型号AD8315_06的Datasheet PDF文件第5页浏览型号AD8315_06的Datasheet PDF文件第6页浏览型号AD8315_06的Datasheet PDF文件第7页 
AD8315  
SPECIFICATIONS  
VS = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.  
Table 1.  
Parameter  
Conditions  
Min Typ  
Max Unit  
OVERALL FUNCTION  
Frequency Range1  
Input Voltage Range  
Equivalent ꢀdm Range  
Logarithmic Slope2  
Logarithmic Intercept2  
Equivalent ꢀdm Level  
RF INPUT INTERFACE  
Input Resistance3  
Input Capacitance3  
OUTPUT  
To meet all specifications  
1 ꢀd log conformance, 0.1 GHz  
0.1  
−57  
−44  
21.5 24  
−79 −70  
−66 −57  
2.5  
−11 ꢀdV  
+2 ꢀdm  
25.5 mV/ꢀd  
−64 ꢀdV  
GHz  
0.1 GH  
0.1 GHz  
−51 ꢀdm  
Pin RFIN  
0.1 GHz  
0.1 GHz  
2.8  
0.9  
kΩ  
pF  
Pin VAPC  
Minimum Output Voltage  
VSET ≤ 200 mV, ENdL high  
ENdL low  
RL ≥ 800 Ω  
85°C, VPOS = 3 V, IOUT = 6 mA  
2.7 V ≤ VPOS ≤ 5.5 V, RL = ∞  
Source/Sink  
0.25 0.27  
0.02  
2.45  
0.3  
2.6  
V
V
V
V
Maximum Output Voltage  
vs. Temperature4  
General Limit  
Output Current Drive  
Output duffer Noise  
Output Noise  
Small Signal danꢀwiꢀth  
Slew Rate  
2.54  
VPOS − 0.1  
5/200  
25  
130  
30  
13  
V
mA/μA  
nV√Hz  
nV/√Hz  
MHz  
V/μs  
ns  
RF input = 2 GHz, 0 ꢀdm, fNOISE = 100 kHz, CFLT = 220 pF  
0.2 V to 2.6 V swing  
10% to 90%, 1.2 V step (VSET), open loop5  
Response Time  
FLTR = open, see Figure 26  
150  
SETPOINT INTERFACE  
Nominal Input Range  
Logarithmic Scale Factor  
Input Resistance  
Pin VSET  
Corresponꢀing to central 50 ꢀd  
0.25  
1.8  
1.4  
V
ꢀd/V  
kΩ  
43.5  
100  
16  
Slew Rate  
V/μs  
ENAdLE INTERFACE  
Logic Level to Enable Power  
Pin ENdL  
VPOS  
V
Input Current when Enable  
High  
20  
μA  
Logic Level to Disable Power  
Enable Time  
0.8  
5
V
μs  
Time from ENdL high to VAPC within 1% of final value,  
VSET ≤ 200 mV, refer to Figure 23  
4
Disable Time  
Time from ENdL low to VAPC within 1% of final value,  
VSET ≤ 200 mV, refer to Figure 23  
Time from VPOS/ENdL high to VAPC within 1% of final value,  
8
9
μs  
μs  
ns  
Power-On/Enable Time  
2
3
V
SET ≤ 200 mV, refer to Figure 28  
Time from VPOS/ENdL low to VAPC within 1% of final value,  
VSET ≤ 200 mV, refer to Figure 28  
100  
200  
Rev. C | Page 3 of 24  
 

与AD8315_06相关器件

型号 品牌 描述 获取价格 数据表
AD8315_16 ADI 50 dB GSM PA Controller

获取价格

AD8315ACHIPS ADI 50 dB GSM PA Controller

获取价格

AD8315ACP-EVAL ADI 50 dB GSM PA Controller

获取价格

AD8315ACP-EVALZ ADI 50 dB GSM PA Controller

获取价格

AD8315ACP-REEL ADI 50 dB GSM PA Controller

获取价格

AD8315ACP-REEL7 ADI 50 dB GSM PA Controller

获取价格