Datasheet > AD80141BCPZ-140

AD80141BCPZ-140

更新时间： 2024-01-17 21:09:00

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
44页	958K
描述
12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter

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技术参数
数据手册

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AD80141BCPZ-140 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	CSP
包装说明：	,	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.63
转换器类型：	ADC, FLASH METHOD	JESD-609代码：	e3
湿度敏感等级：	3	输出位码：	OFFSET BINARY
端子面层：	Matte Tin (Sn)	Base Number Matches：	1

AD80141BCPZ-140 数据手册

AD9233

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS enabled, unless otherwise noted.

Table 1.

AD9233BCPZ-80

AD9233BCPZ-105

AD9233BCPZ-125

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

2ꢀ°C

Full

2ꢀ°C

Guaranteed

±±.3

±±.2

±±.ꢀ

±4.ꢂ

±±.3

±±.2

±±.ꢁ

±4.ꢃ

±±.ꢀ

±±.3

±±.2

±±.ꢁ

±3.ꢃ

±±.ꢀ

% FSR

LSB

Differential Nonlinearity (DNL)¹

±±.2

±±.ꢀ

±±.2

±±.ꢀ

±±.2

±±.ꢀ

Integral Nonlinearity (INL)¹

±1.2

±2±

±1.2

±3ꢀ

±1.2

±3ꢀ

LSB

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±1ꢀ

±ꢃꢀ

±1ꢀ

±ꢃꢀ

±1ꢀ

±ꢃꢀ

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.± mA

INPUT REFERRED NOISE

VREF = 1.± V

Full

±ꢀ

ꢂ

±ꢀ

ꢂ

±ꢀ

ꢂ

2ꢀ°C

±.34

LSB rms

ANALOG INPUT

Input Span, VREF = 1.± V

Input Capacitance²

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Full

ꢁ

V p-p

kΩ

Supply Voltage

AVDD

DRVDD

Full

1.ꢂ

1.ꢁ

3.3

1.ꢃ

3.6

1.ꢂ

1.ꢁ

3.3

1.ꢃ

3.6

1.ꢂ

1.ꢁ

3.3

1.ꢃ

3.6

Supply Current

IAVDD¹

Full

13ꢁ

ꢂ

1ꢀꢀ

1ꢂꢁ

ꢁ

1ꢃ4

22±

1±

1ꢂ

236

IDRVDD¹(DRVDD = 1.ꢁ V)

IDRVDD¹(DRVDD = 3.3 V)

POWER CONSUMPTION

DC Input

Full

24ꢁ

261

2ꢁꢁ

4±

2ꢂꢃ

32±

33ꢀ

36ꢀ

4±

3ꢀ±

3ꢃꢀ

41ꢀ

4ꢀ2

4±

42ꢀ

Sine Wave Input¹(DRVDD = 1.ꢁ V)

Sine Wave Input¹(DRVDD = 3.3 V)

Standby³

Power-Down

1.ꢁ

¹Measured with a low input frequency, full-scale sine wave, with approximately ꢀ pF loading on each output bit.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

³Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Rev. A | Page 4 of 44

1 2 345 6 7...44

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