AD7874BQ

更新时间： 2024-01-09 14:55:12

品牌	Logo	应用领域
亚德诺 - ADI		转换器信息通信管理
页数	文件大小	规格书
16页	417K
描述
LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System

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AD7874BQ 技术参数

Source Url Status Check Date：	2013-05-01 14:56:21.354	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	DIP	包装说明：	DIP, DIP28,.6
针数：	28	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	1.54	Is Samacsys：	N
最大模拟输入电压：	15 V	最小模拟输入电压：	10 V
最长转换时间：	35 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-GDIP-T28	JESD-609代码：	e0
长度：	37.84 mm	最大线性误差 (EL)：	0.024%
标称负供电电压：	-5 V	模拟输入通道数量：	4
位数：	12	功能数量：	1
端子数量：	28	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	2'S COMPLEMENT BINARY
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP28,.6	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	+-5 V	认证状态：	Not Qualified
采样速率：	0.029 MHz	采样并保持/跟踪并保持：	TRACK
筛选级别：	MIL-STD-883 Class B	座面最大高度：	5.59 mm
子类别：	Analog to Digital Converters	最大压摆率：	18 mA
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT APPLICABLE	宽度：	13.2 mm
Base Number Matches：	1

AD7874BQ 数据手册

AD7874

Gain error can be adjusted at either the first code transition

(ADC negative full scale) or the last code transition (ADC posi-

tive full scale). T he trim procedures for both cases are as

follows:

OUTPUT

CODE

011...111

011...110

P ositive Full-Scale Adjust

Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V₁. Adjust

R2 until the ADC output code flickers between 0111 1111 1110

and 0111 1111 1111.

000...010

000...001

000...000

–

Negative Full-Scale Adjust

– 1LSB

111...111

111...110

Apply a voltage of –9.9976 V ( –FS + 1/2 LSB) at V₁and adjust

R2 until the ADC output code flickers between 1000 0000 0000

and 1000 0000 0001.

FS=20V

1LSB =

4096

100...001

100...000

An alternative scheme for adjusting full-scale error in systems

which use an external reference is to adjust the voltage at the

REF IN pin until the full-scale error for any of the channels is

adjusted out. T he good full-scale matching of the channels will

ensure small full-scale errors on the other channels.

INPUT VOLTAGE

Figure 5. Input/Output Transfer Function

TIMING AND CO NTRO L

Conversion is initiated on the AD7874 by asserting the

CONVST input. T his CONVST input is an asynchronous input

which is independent of the ADC clock. T his is essential for

applications where precise sampling in time is important. In

these applications, the signal sampling must occur at exactly

equal intervals to minimize errors due to sampling uncertainty

or jitter. In these cases, the CONVST input is driven from a

timer or precise clock source. Once conversion is started,

CONVST should not be asserted again until conversion is com-

plete on all four channels.

O FFSET AND FULL-SCALE AD JUSTMENT

In most Digital Signal Processing (DSP) applications, offset and

full-scale errors have little or no effect on system performance.

Offset error can always be eliminated in the analog domain by

ac coupling. Full-scale error effect is linear and does not cause

problems as long as the input signal is within the full dynamic

range of the ADC. Invariably, some applications will require

that the input signal span the full analog input dynamic range.

In such applications, offset and full-scale error will have to be

adjusted to zero.

In applications where precise time interval sampling is not criti-

cal, the CONVST pulse can be generated from a microproces-

sor WRIT E or READ line gated with a decoded address

(different to the AD7874 CS address). CONVST should not be

derived from a decoded address alone because very short

CONVST pulses (which may occur in some microprocessor sys-

tems as the address bus is changing at the start of an instruction

cycle) could initiate a conversion.

Figure 6 shows a circuit which can be used to adjust the offset

and full-scale errors on the AD7874 (Channel 1 is shown for ex-

ample purposes only). Where adjustment is required, offset er-

ror must be adjusted before full-scale error. T his is achieved by

trimming the offset of the op amp driving the analog input of

the AD7874 while the input voltage is a 1/2 LSB below analog

ground. T he trim procedure is as follows: apply a voltage of

–2.44 mV (–1/2 LSB) at V₁in Figure 6 and adjust the op amp

offset voltage until the ADC output code flickers between 1111

1111 1111 and 0000 0000 0000.

All four track/hold amplifiers go from track to hold on the rising

edge of the CONVST pulse. T he four track/hold amplifiers re-

main in their hold mode while all four channels are converted.

T he rising edge of CONVST also initiates a conversion on the

Channel 1 input voltage (V_IN1). When conversion is complete

on Channel 1, its result is stored in Data Register 1, one of four

on-chip registers used to store the conversion results. When the

result from the first conversion is stored, conversion is initiated

on the voltage held by track/hold 2. When conversion has been

completed on the voltage held by track/hold 4 and its result is

stored in Data Register 4, INT goes low to indicate that the

conversion process is complete.

INPUT

RANGE = ±10V

10kΩ

500Ω

IN1

10kΩ

AD7874*

10kΩ

T he sequence in which the channel conversions takes place is

automatically taken care of by the AD7874. T his means that the

user does not have to provide address lines to the AD7874 or

worry about selecting which channel is to be digitized.

AGND

Reading data from the device consists of four read operations to

the same microprocessor address. Addressing of the four

on-chip data registers is again automatically taken care of by the

AD7874.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 6. AD7874 Full-Scale Adjust Circuit

REV. C

–7–

1...4 5 678 9 10...16

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与AD7874BQ相关器件

型号	品牌	描述	获取价格	数据表
AD7874BQ/883B	ADI	ADC, Successive Approximation	获取价格
AD7874BR	ADI	LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System	获取价格
AD7874BR	ROCHESTER	4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, SOIC-28	获取价格
AD7874BR-REEL	ADI	IC 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, SOIC-28, Analog to D	获取价格
AD7874BRZ	ADI	暂无描述	获取价格
AD7874BRZ-REEL	ADI	4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, SOIC-28	获取价格

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