AD7819
TIMING CHARACTERISTICS1, 2
(–40ꢂC to +125ꢂC, unless otherwise noted)
Parameter
VDD = 3 V ꢁ 10%
VDD = 5 V ꢁ 10%
Units
Conditions/Comments
tPOWER-UP
1
1
µs (max)
µs (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
Power-Up Time of AD7819 after Rising Edge of CONVST.
Conversion Time.
CONVST Pulsewidth.
CONVST Falling Edge to BUSY Rising Edge Delay.
CS to RD Setup Time.
CS Hold Time after RD High.
Data Access Time after RD Low.
Bus Relinquish Time after RD High.
Data Bus Relinquish to Falling Edge of CONVST Delay.
t1
t2
t3
t4
t5
4.5
30
30
0
4.5
30
30
0
0
0
3
t6
t7
10
10
100
10
10
100
3, 4
3
t8
NOTES
1Sample tested to ensure compliance.
2See Figures 12, 13 and 14.
3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V 10% and
0.4 V or 2 V for VDD = 3 V 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND
I
200ꢀA
OL
(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND
TO
OUTPUT
PIN
+1.6V
C
L
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
50pF
200ꢀA
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . .+260°C
ORDERING GUIDE
Linearity
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Error
(LSB)
Package
Description
Package
Option
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
Model
AD7819YN
AD7819YR
AD7819YRU
1 LSB
1 LSB
1 LSB
Plastic DIP
Small Outline IC
Thin Shrink Small Outline RU-16
(TSSOP)
N-16
R-16A
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
–3–
REV. A
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