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AD7742BR-REEL PDF预览

AD7742BR-REEL

更新时间： 2024-02-28 12:03:33
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亚德诺 - ADI 转换器
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AD7741/AD7742  
(VDD = +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to  
MAX unless otherwise noted.)  
AD7742–SPECIFICATIONS T  
B Version1  
Y Version2  
Parameter3  
Min  
Typ  
Max  
Min  
Typ  
Max  
Units  
Conditions/Comments  
DC PERFORMANCE  
Integral Nonlinearity  
fCLKIN = 200 kHz4  
fCLKIN = 3 MHz4  
fCLKIN = 6.144 MHz  
Offset Error  
±0.0122  
±0.0122  
±0.0122  
±40  
±0.015  
±0.015  
±0.015  
±40  
% of Span5  
% of Span  
% of Span  
mV  
Unipolar Mode  
Bipolar Mode  
Unipolar Mode  
Bipolar Mode  
Unipolar Mode  
Bipolar Mode  
Unipolar Mode  
Bipolar Mode  
∆VDD = ±5%  
±40  
+2.2  
+2.2  
±40  
+2.2  
+2.2  
mV  
Gain Error  
+0.2  
+0.2  
+1.2  
+1.2  
±12  
±12  
±2  
+0.2  
+0.2  
+1.2  
+1.2  
±12  
±12  
±2  
% of Span  
% of Span  
µV/°C  
Offset Error Drift4  
Gain Error Drift4  
µV/°C  
ppm of Span/°C  
ppm of Span/°C  
dB  
dB  
dB  
±4  
±4  
Power Supply Rejection Ratio4  
Channel-to-Channel Isolation4  
Common-Mode Rejection  
–70  
–75  
–78  
–70  
–75  
–78  
–60  
–58  
ANALOG INPUTS (VIN1–VIN4)6  
Input Current  
Common-Mode Input Range  
Differential Input Range  
±50  
±100  
±50  
±100  
nA  
V
V
+0.5  
–VREF/Gain  
0
V
DD – 1.75 +0.5  
VDD – 1.75  
+VREF/Gain  
+VREF/Gain  
+VREF/Gain –VREF/Gain  
+VREF/Gain  
Bipolar Mode  
Unipolar Mode  
0
V
VOLTAGE REFERENCE  
REFIN  
Nominal Input Voltage  
Input Impedance4  
fCLKIN = 3 MHz  
fCLKIN = 6.144 MHz  
REFOUT  
2.5  
2.5  
V
70  
35  
70  
35  
kΩ  
kΩ  
Output Voltage  
2.38  
2.50  
1
±50  
–70  
2.60  
2.38  
2.50  
1
±50  
–70  
2.60  
V
kΩ  
ppm/°C  
dB  
Output Impedance4  
Reference Drift4  
Line Rejection  
Reference Noise  
(0.1 Hz to 10 Hz)4  
100  
100  
µV p-p  
LOGIC OUTPUT  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Minimum Output Frequency  
4.0  
4.0  
V
V
Hz  
Output Sourcing 800 µA7  
Output Sinking 1.6 mA7  
VIN = 0 V (Unipolar), VIN  
–VREF/Gain (Bipolar)  
VIN = VREF/Gain (Unipolar  
and Bipolar)  
0.4  
0.4  
0.05 fCLKIN  
0.45 fCLKIN  
0.05 fCLKIN  
0.45 fCLKIN  
=
Maximum Output Frequency  
Hz  
LOGIC INPUT  
ALL EXCEPT CLKIN  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current  
Pin Capacitance  
CLKIN ONLY  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current  
2.4  
3.5  
2.4  
3.5  
V
V
nA  
pF  
0.8  
±100  
10  
0.8  
±100  
10  
6
6
6
6
V
V
µA  
pF  
0.8  
±2  
10  
0.8  
±2  
10  
Pin Capacitance  
CLOCK FREQUENCY  
Input Frequency  
6.144  
6.144  
MHz  
For Specified Performance  
Output Unloaded  
POWER REQUIREMENTS  
VDD  
IDD (Normal Mode)  
IDD (Power-Down)  
Power-Up Time4  
4.75  
5.25  
8
35  
4.75  
5.25  
8
35  
V
6
25  
30  
6
25  
30  
mA  
µA  
µs  
Coming Out of Power-  
Down Mode  
N
OTES  
1Temperature range: B Version: –40°C to +85°C.  
2Temperature range: Y Version: –40°C to +105°C.  
3See Terminology.  
4Guaranteed by design and characterization, not production tested.  
5Span = Maximum Output Frequency–Minimum Output Frequency.  
6The absolute voltage on the input pins must not go more positive than VDD – 1.75 V or more negative than +0.5 V.  
7These logic levels apply to CLKOUT only when it is loaded with one CMOS load.  
Specifications subject to change without notice  
.
REV. 0  
–3–  
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