AD7741/AD7742
AD7742 PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
Function
1
2
fOUT
VDD
Frequency Output. This pin provides the output of the synchronous VFC.
Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be
adequately decoupled to GND.
3
GND
Ground reference point for all circuitry on the part.
4–5
6
A1, A0
CLKOUT
Address Inputs used to select the input channel configuration.
External Clock Output. When the master clock for the device is a crystal, the crystal is connected be-
tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin
provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source
elsewhere in the system.
7
CLKIN
External Clock Input. The master clock for the device can be provided in the form of a crystal or an
external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN
pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the
master clock may be as high as 6 MHz.
8
UNI/BIP
REFOUT
REFIN
Control input which determines whether the device operates with differential bipolar analog input
signals or differential unipolar analog input signals.
2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a reference
to other parts of the system provided it is buffered first.
This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V reference
is required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci-
sion external reference (e.g., REF192).
9
10
11
12
13
14
VIN1
VIN2
VIN3
VIN4
Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to VIN4 or it is
the positive input of a truly-differential input pair with respect to VIN2.
Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to VIN4 or it is
the negative input of a truly-differential input pair with respect to VIN1.
Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re-
spect to VIN4.
Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respect
to VIN1 or VIN2 or it is the negative input of a truly-differential input pair with respect to VIN3.
15
16
GAIN
PD
Gain Select input that controls whether the gain on the analog front-end is X1 or X2.
Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typi-
cally consumes 25 µA of current.
PIN CONFIGURATION
f
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PD
OUT
V
GAIN
DD
GND
A1
V
V
V
V
4
3
2
1
IN
IN
IN
AD7742
TOP VIEW
(Not to Scale)
A0
CLKOUT
CLKIN
IN
REFIN
UNI/BIP
REFOUT
–6–
REV. 0
5秒后页面跳转
TLP250光耦合器：资料手册参数分析
DA14580 低功耗蓝牙系统级芯片(SoC)：资料手册参数分析
INA226 高精度电流和功率监控器：资料手册参数分析
SI2302 N沟道MOSFET：资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
