Datasheet > AD7741_15

AD7741_15

更新时间： 2022-02-26 14:01:18

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	135K
描述
Single and Multichannel, Synchronous Voltage-to-Frequency Converters

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数据手册

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AD7741_15 数据手册

(V_DD= +4.75 V to +5.25 V; V_REF= +2.5 V; f_CLKIN= 6.144 MHz; all specifications T_MINto

_MAXunless otherwise noted.)

AD7741–SPECIFICATIONS

B and Y Version¹

Parameter²

Min

Typ

Max

Units

Conditions/Comments

DC PERFORMANCE

Integral Nonlinearity

f_CLKIN= 200 kHz³

f_CLKIN= 3 MHz³

±0.012

±0.024

±40

% of Span⁴

% of Span

_CLKIN= 6.144 MHz

V_DD> 4.8 V

Offset Error

Gain Error

+0.8

±30

±16

–63

+1.6

% of Span

µV/°C

ppm of Span/°C

Offset Error Drift³

Gain Error Drift³

Power Supply Rejection Ratio³

∆V_DD= ±5%

ANALOG INPUT⁵

Input Current

Input Voltage Range

±50

±100

V_REF

+2.5 V REFERENCE (REFIN/OUT)

REFIN

Nominal Input Voltage

2.5

N/A

Input Impedance⁶

REFOUT

Output Voltage

2.38

4.0

2.50

±50

–60

100

2.60

0.4

kΩ

ppm/°C

µV p-p

Output Impedance³

Reference Drift³

Line Rejection

Reference Noise (0.1 Hz to 10 Hz)³

LOGIC OUTPUT

Output High Voltage, V_OH

Output Low Voltage, V_OL

Minimum Output Frequency

Maximum Output Frequency

Output Sourcing 800 µA⁷

Output Sinking 1.6 mA⁷

V_IN= 0 V

0.05 f_CLKIN

0.45 f_CLKIN

V_IN= V_REF

LOGIC INPUT

PD ONLY

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Current

Pin Capacitance

CLKIN ONLY

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Current

2.4

3.5

0.8

±100

µA

0.8

±2

Pin Capacitance

CLOCK FREQUENCY

Input Frequency

6.144

MHz

For Specified Performance

POWER REQUIREMENTS

V_DD

4.75

5.25

_DD(Normal Mode)

_DD(Power-Down)

µA

µs

Output Unloaded

Power-Up Time³

Coming Out of Power-Down Mode

NOTES

¹Temperature ranges: B Version –40°C to +85°C: Y Version: –40°C to +105°C.

²See Terminology.

³Guaranteed by design and characterization, not production tested.

⁴Span = Maximum Output Frequency–Minimum Output Frequency.

⁵The absolute voltage on the input pin must not go more positive than V_DD– 2.25 V or more negative than GND.

⁶Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 µA in order to overdrive the internal reference.

⁷These logic levels apply to CLKOUT only when it is loaded with one CMOS load.

Specifications subject to change without notice.

–2–

REV. 0

123 4 5 6 7...12

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