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AD7376ARWZ50

更新时间： 2024-02-04 19:44:00
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 452K
描述
128-Position Digital Potentiometer

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AD7376ARWZ50 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：2.35
Samacsys Description：AD7376ARWZ50, Digital Potentiometer 50kΩ 128-Position Serial-3 Wire, Serial-SPI 16-Pin SOIC W其他特性：IT CAN ALSO OPERATE FRON 4.5 TO 33V SINGLE SUPPLY
标称带宽：0.09 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：1标称负供电电压：-5 V
功能数量：1位置数：128
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：+-5/+-15 V
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：30%最大电阻器端电压：5 V
最小电阻器端电压：-5 V座面最大高度：2.65 mm
子类别：Digital Potentiometers标称供电电压：5 V
表面贴装：YES技术：CMOS
标称温度系数：35 ppm/ °C温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30标称总电阻：50000 Ω
宽度：7.5 mm

AD7376ARWZ50 数据手册

 浏览型号AD7376ARWZ50的Datasheet PDF文件第2页浏览型号AD7376ARWZ50的Datasheet PDF文件第3页浏览型号AD7376ARWZ50的Datasheet PDF文件第4页浏览型号AD7376ARWZ50的Datasheet PDF文件第6页浏览型号AD7376ARWZ50的Datasheet PDF文件第7页浏览型号AD7376ARWZ50的Datasheet PDF文件第8页 
AD7376  
Parameter  
Symbol  
Conditions  
Min  
2.4  
Typ 1 Max  
Unit  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
Input Logic Low  
VIH  
VIL  
VOH  
VOL  
IIL  
VDD = 5 V or 15 V  
VDD = 5 V or 15 V  
RPull-Up = 2.2 kΩ to 5 V  
IOL = 1.6 mA, VDD = 15 V  
VIN = 0 V or 5 V  
V
V
V
V
µA  
pF  
0.8  
Output Logic High  
Output Logic Low  
Input Current  
Input Capacitance6  
POWER SUPPLIES  
Power Supply Range  
Power Supply Range  
Positive Supply Current  
4.9  
0.4  
1
CIL  
5
VDD/VSS  
VDD  
IDD  
Dual-supply range  
Single-supply range, VSS = 0  
4.5  
4.5  
16.5  
33  
2
V
V
VIH = 5 V or VIL = 0 V, VDD/VSS = 15 V  
VIH = 5 V or VIL = 0 V, VDD/VSS = 5 V  
VIH = 5 V or VIL = 0 V, VDD/VSS = 15 V  
VIH = 5 V or VIL = 0 V, VDD/VSS = 5 V  
VIH = 5 V or VIL = 0 V, VDD/VSS = 15 V  
mA  
µA  
mA  
mA  
mW  
12  
25  
Negative Supply Current  
ISS  
−0.1  
−0.1  
31.5  
Power Dissipation8  
PDISS  
Power Supply Rejection Ratio  
DYNAMIC CHARACTERISTICS6, 9, 10  
Bandwidth −3 dB  
PSRR  
−0.25  
0.1  
+0.25 %/%  
BW  
RAB = 50 kΩ, code = 0x40  
90  
50  
0.002  
4
kHz  
kHz  
%
µs  
nV√Hz  
RAB = 100 kΩ, code = 0x40  
VA = 1 V rms, VB = 0 V, f = 1 kHz  
VA = 10 V, VB = 0 V, 1 LSB error band  
RWB = 25 kΩ, f = 1 kHz  
Total Harmonic Distortion  
VW Settling Time  
Resistor Noise Voltage  
THDW  
tS  
eN_WB  
2
1 Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL  
measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.  
3 Pb-free parts have a 35 ppm/°C temperature coefficient.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
7 Measured at the A terminal. A terminal is open circuit in shutdown mode.  
8 PDISS is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation.  
9 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest  
bandwidth. The highest R value results in the minimum overall power consumption.  
10 All dynamic characteristics use VDD = 15 V and VSS = −15 V.  
TIMING SPECIFICATIONS  
Table 3.  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
INTERFACE TIMING CHARACTERISTICS1, 2  
Clock Frequency  
Input Clock Pulse Width  
Data Setup Time  
fCLK  
tCH, tCL  
tDS  
tDH  
tPD  
tCSS  
tCSW  
tRS  
tCSH0  
tCSH  
tCS1  
4
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock level high or low  
RPull-Up = 2.2 kΩ, CL < 20 pF  
120  
30  
20  
Data Hold Time  
CLK to SDO Propagation Delay3  
CS Setup Time  
10  
100  
120  
150  
120  
10  
CS High Pulse Width  
Reset Pulse Width  
CLK Fall to CS Fall Hold Time  
CLK Rise to CS Rise Hold Time  
CS Rise to Clock Rise Setup  
120  
120  
1 Guaranteed by design and not subject to production test.  
2 See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
Switching characteristics are measured using VDD = 15 V and VSS = −15 V.  
3 Propagation delay depends on value of VDD, RPull-Up, and CL.  
Rev. D | Page 5 of 20  
 
 
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