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AD7280WDCPZ PDF预览

AD7280WDCPZ

更新时间： 2024-01-26 12:43:53
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
38页 435K
描述
IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48, LEAD FREE, MO-220WKKD, LFCSP-48, Power Management Circuit

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AD7280WDCPZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：LEAD FREE, MO-220WKKD, LFCSP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.83可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：S-XQCC-N48
长度：7 mm信道数量：6
功能数量：1端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源：7.5/30 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：Power Management Circuits最大供电电流 (Isup)：10 mA
最大供电电压 (Vsup)：30 V最小供电电压 (Vsup)：7.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：7 mmBase Number Matches：1

AD7280WDCPZ 数据手册

 浏览型号AD7280WDCPZ的Datasheet PDF文件第3页浏览型号AD7280WDCPZ的Datasheet PDF文件第4页浏览型号AD7280WDCPZ的Datasheet PDF文件第5页浏览型号AD7280WDCPZ的Datasheet PDF文件第7页浏览型号AD7280WDCPZ的Datasheet PDF文件第8页浏览型号AD7280WDCPZ的Datasheet PDF文件第9页 
Preliminary Technical Data  
AD7280  
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VIN6  
CB6  
VIN5  
CB5  
VIN4  
CB4  
VIN3  
CB3  
VIN2  
CB2  
VIN1  
CB1  
VT3  
VIN6  
CB6  
VIN5  
CB5  
VIN4  
CB4  
VIN3  
CB3  
VIN2  
1
2
3
4
5
6
7
8
9
36 VT3  
PIN 1  
INDICATOR  
PIN 1  
VT4  
35 VT4  
34 VT5  
3
VT5  
33 VT6  
4
VT6  
32 VTTERM  
31 AGND  
30 AVCC  
29 VDRIVE  
28 ALERTlo  
27 ALERT  
26 SDO  
5
VTTERM  
AGND  
AVCC  
VDRIVE  
ALERTlo  
ALERT  
SDO  
AD7280  
TOP VIEW  
AD7280  
TOP VIEW  
6
7
8
CB2 10  
VIN1 11  
CB1 12  
9
10  
11  
12  
25 SDOlo  
SDOlo  
13 14 15 16 17 18 19 20 21 22 23 24  
Figure 3.  
Figure 2.  
Table 4.  
Pin No.  
Mnemonic Description  
1, 3, 5, 7,  
9, 11, 13  
Vin6 to  
Vin0  
Analog Input 0 to Analog Input 6. Analog input 0 should be connected to the base of the series connected  
battery cells. Analog Input 1 should be connected to the top of cell 1, Analog Input 2 should be connected to  
the top of cell 2, etc. The Analog Inputs are multiplexed into the on-chip track-and-hold allowing the potential  
across each cell to be measured.  
2, 4, 6, 8,  
10, 12  
CB6 to CB1 Cell Balance Outputs. These provide a voltage output which can be used to supply the gate drives of a cell  
balancing transistor network. Each CB(n) output provides a 5V voltage output referenced to the absolute  
voltage of Cell(n-1).  
14  
MASTER  
Voltage Input. In an application with 2 or more AD7280s Daisy Chained the MASTER pin of the AD7280  
connected directly to the DSP or uP should be connected to the VDD supply pin through a 10kOhm resistor. The  
MASTER pin on the remaining AD7280s in the application should be tied to their respective VSS supply pins  
through 10kOhm resistors.  
15  
16  
PD  
Power down Input. This input is used to power down the AD7280. When acting as master the PD input is  
supplied from the DSP/uP. When acting as a slave on the Daisy Chain the PD input should be connected to the  
PDhi output of the AD7280 immediately below it in potential in the Daisy Chain.  
VDD  
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure  
AD7280. The supply must be greater than a minimum voltage of 7.5 V. In an application monitoring the cell  
voltages of up to 6 series connected battery cells the supply voltage may be supplied directly from the cell with  
the highest potential. The maximum voltage which can be applied between VDD and VSS is 30V. Place 10 µF and  
100 nF decoupling capacitors on the VDD pin.  
17  
18  
VSS  
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure  
of the AD7280. This input should be at the same potential as the AGND voltage.  
Analog Voltage output, 5V. The internally generated VREG voltage, which provides the supply voltage for the  
ADC core, is available on this pin for use external to the AD7280. Place 10 µF and 100 nF decoupling capacitors  
on the VREG pin.  
VREG  
19  
20  
DVCC  
Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.  
For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the  
voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled  
to DGND. Place 100 nF decoupling capacitors on the DVCC pin. The DVCC supply pin should be connected to the  
V
REG output  
DGND  
Digital Ground. Ground reference point for all digital circuitry on the AD7280. The DGND and AGND voltages  
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.  
Rev. PrF | Page 6 of 38  
1...3456789...38

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