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AD7274BRM PDF预览

AD7274BRM

更新时间: 2024-01-04 23:04:29
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 235K
描述
3MSPS,10-/12-Bit ADCs in 8-Lead TSOT

AD7274BRM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:MO-193BA, TSOT-8针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.38
最大模拟输入电压:2.5 V最小模拟输入电压:
最长转换时间:0.27 µs转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:2.9 mm最大线性误差 (EL):0.0244%
模拟输入通道数量:1位数:12
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSSOP8,.1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5/3.3 V认证状态:Not Qualified
采样速率:3 MHz采样并保持/跟踪并保持:TRACK
座面最大高度:1 mm子类别:Analog to Digital Converters
标称供电电压:3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.6 mmBase Number Matches:1

AD7274BRM 数据手册

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PRELIMINARYTECHNICALDATA  
Preliminary Technical Data  
AD7273/AD7274  
Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.  
t1  
tconvert  
t2  
t6  
B
SCLK  
3
1
2
4
5
13  
15  
16  
14  
t5  
t7  
t8  
tquiet  
t3  
t4  
DB9  
DB1  
Z
ZERO  
DB11  
DB10  
DB0  
ZERO  
ZERO  
SDATA  
THREE-  
STATE  
THREE-STATE  
2 TRAILING  
ZEROS  
2 LEADING  
ZERO’S  
1/ THROUGHPUT  
Figure 5. AD7274 Serial Interface Timing Diagram  
Timing Example 1  
From Figure 6, having fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ  
333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ  
=
.
Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD  
ns for tQUIET satisfying the minimum requirement of TBD ns.  
Timing Example 2  
Having fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns.  
With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. From  
Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for  
tQUIET satisfying the minimum requirement of TBD ns.  
t1  
tconvert  
t2  
B
SCLK  
3
4
5
1
2
14  
15  
16  
12  
13  
t8  
tquiet  
12.5(1/fSCLK)  
tacquisition  
1/THROUGHPUT  
Figure 6. Serial Interface Timing Example  
REV. PrB  
7–  

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