AD7224
VOUT = D • VREF
TERMINO LO GY
TO TAL UNAD JUSTED ERRO R
where D is a fractional representation of the digital input code
T otal Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy and zero code error.
Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. T he LSB size will vary over the VREF range.
Hence the zero code error, relative to the LSB size, will increase
as VREF decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the VREF range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
and can vary from 0 to 255/256.
O P -AMP SECTIO N
T he voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is
capable of developing +10 V across a 2 kΩ load and can drive
capacitive loads of 3300 pF.
T he AD7224 can be operated single or dual supply resulting in
different performance in some parameters from the output am-
plifier. In single supply operation (VSS = 0 V = AGND) the sink
capability of the amplifier, which is normally 400 µA, is reduced
as the output voltage nears AGND. T he full sink capability of
400 µA is maintained over the full output voltage range by tying
VSS to –5 V. T his is indicated in Figure 2.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
500
D IFFERENTIAL NO NLINEARITY
V
= –5V
SS
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
400
300
200
100
0
V
T
= +15V
= 25°C
DD
V
= 0V
SS
A
D IGITAL FEED TH RO UGH
Digital Feedthrough is the glitch impulse transferred to the out-
put due to a change in the digital input code. It is specified in
nV secs and is measured at VREF = 0 V.
4
6
8
10
0
2
FULL-SCALE ERRO R
Full-Scale Error is defined as:
V
– Volts
OUT
Measured Value – Zero Code Error – Ideal Value
Figure 2. Variation of ISINK with VOUT
Settling-time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by VSS.
CIRCUIT INFO RMATIO N
D /A SECTIO N
T he AD7224 contains an 8-bit voltage-mode digital-to-analog
converter. T he output voltage from the converter has the same
polarity as the reference voltage, allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7224 al-
lows a reference voltage range from +2 V to +12.5 V.
Additionally, the negative VSS gives more headroom to the out-
put amplifier which results in better zero code performance and
improved slew-rate at the output, than can be obtained in the
single supply mode.
T he DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS single pole, double-throw switches.
T he simplified circuit diagram for this DAC is shown in
Figure 1.
D IGITAL SECTIO N
T he AD7224 digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. T o minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practi-
cally possible.
R
R
R
VOUT
2R
2R
DB0
2R
DB0
2R
DB0
2R
DB0
VREF
SHOWN FOR ALL 1's ON DAC
AGND
INTERFACE LO GIC INFO RMATIO N
Figure 1. D/A Sim plified Circuit Diagram
T able I shows the truth table for AD7224 operation. T he part
contains two registers, an input register and a DAC register. CS
and WR control the loading of the input register while LDAC
and WR control the transfer of information from the input regis-
ter to the DAC register. Only the data held in the DAC register
will determine the analog output of the converter.
T he input impedance at the VREF pin is code dependent and can
vary from 8 kΩ minimum to infinity. T he lowest input imped-
ance occurs when the DAC is loaded with the digital code
01010101. T herefore, it is important that the reference presents
a low output impedance under changing load conditions. T he
nodal capacitance at the reference terminals is also code depen-
dent and typically varies from 25 pF to 50 pF.
All control signals are level-triggered and therefore either or
both registers may be made transparent; the input register by
keeping CS and WR “LOW”, the DAC register by keeping
LDAC and WR “LOW”. Input data is latched on the rising
edge of WR.
T he VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
–5–
REV. B
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