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AD680AN

更新时间： 2024-02-28 09:14:01
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 163K
描述
Low Power, Low Cost 2.5 V Reference

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AD680AN 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TO-92
包装说明：, SIP3,.1,50针数：3
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.49
模拟集成电路 - 其他类型：THREE TERMINAL VOLTAGE REFERENCEJESD-30 代码：O-MBCY-W3
JESD-609代码：e3湿度敏感等级：1
功能数量：1输出次数：1
端子数量：3最高工作温度：70 °C
最低工作温度：最大输出电压：2.51 V
最小输出电压：2.49 V标称输出电压：2.5 V
封装主体材料：METAL封装等效代码：SIP3,.1,50
封装形状：ROUND封装形式：CYLINDRICAL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
子类别：Voltage References最大供电电流 (Isup)：0.28 mA
最大供电电压 (Vsup)：36 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BIPOLAR最大电压温度系数：30 ppm/ °C
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：WIRE端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
微调/可调输出：NO最大电压容差：0.4%
Base Number Matches：1

AD680AN 数据手册

 浏览型号AD680AN的Datasheet PDF文件第1页浏览型号AD680AN的Datasheet PDF文件第2页浏览型号AD680AN的Datasheet PDF文件第4页浏览型号AD680AN的Datasheet PDF文件第5页浏览型号AD680AN的Datasheet PDF文件第6页浏览型号AD680AN的Datasheet PDF文件第7页 
AD680  
ABSO LUTE MAXIMUM RATINGS*  
TH EO RY O F O P ERATIO N  
VIN to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V  
Power Dissipation (25°C) . . . . . . . . . . . . . . . . . . . . . . 500 mW  
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +125°C  
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . . 300°C  
Package T hermal Resistance  
Bandgap references are the high performance solution for low  
supply voltage operation. A typical precision bandgap will con-  
sist of a reference core and buffer amplifier. Based on a new,  
patented bandgap reference design (Figure 2), the AD680  
merges the amplifier and the core bandgap function to produce  
a compact, complete precision reference. Central to the device  
is a high gain amplifier with an intentionally large Proportional  
T o Absolute T emperature (PT AT ) input offset. T his offset is  
controlled by the area ratio of the amplifier input pair, Q1 and  
Q2, and is developed across resistor R1. T ransistor Q12’s base  
emitter voltage has a Complementary T o Absolute T emperature  
(CT AT ) characteristic. Resistor R2 and the parallel combina-  
tion of R3 and R4 “multiply” the PT AT voltage across R1.  
T rimming resistors R3 and R4 to the proper ratio produces a  
temperature invariant 2.5 V at the output. T he result is an  
accurate, stable output voltage accomplished with a minimum  
number of components.  
θ
JA (All Packages) . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W  
Output Protection: Output safe for indefinite short to ground  
and momentary short to VIN.  
*Stresses above those listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. T his is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
8-P in P lastic D IP  
and  
8-P in SO IC P ackages  
+V  
IN  
1
2
3
4
TP*  
8
7
6
5
TP*  
TP*  
V
+V  
AD680  
TOP VIEW  
(Not to Scale)  
IN  
TEMP  
GND  
Q9  
Q8  
OUT  
NC  
Q11  
Q3  
Q2  
Q4  
V
OUT  
NC = NO CONNECT  
Q5  
Q1  
1x  
*TP DENOTES FACTORY TEST POINT.  
NO CONNECTIONS SHOULD BE MADE  
TO THESE PINS.  
R1  
R2  
R3  
R4  
R5  
8x  
C1  
Q10  
Q12  
TO -92 P ackage  
Q6  
Q7  
R6  
R7  
AD680  
BOTTOM VIEW  
(Not to Scale)  
TEMP  
GND  
3
2
1
Figure 2. AD680 Schem atic Diagram  
+V  
V
GND  
IN  
OUT  
An additional feature with this approach is the ability to mini-  
mize the noise while maintaining very low overall power  
dissipation for the entire circuit. Frequently it is difficult to  
independently control the dominant noise sources for bandgap  
references: bandgap transistor noise and resistor thermal noise.  
By properly choosing the operating currents of Q1 and Q2 and  
separately sizing R1, low wideband noise is realized while main-  
taining 1 mW typical power dissipation.  
Figure 1. Connection Diagram s  
O RD ERING GUID E  
Initial Tem perature  
Error  
m V  
Coeff.  
ppm /°C  
Tem perature  
Range  
P ackage  
D escription  
P ackage  
O ption*  
Model  
AD680JN  
AD680JR  
AD680JT  
AD680AN  
AD680AR  
10  
10  
10  
5
25  
25  
30  
20  
20  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
–40°C to +85°C  
–40°C to +85°C  
Plastic  
SOIC  
T O-92  
Plastic  
SOIC  
N-8  
SO-8  
T O-92  
N-8  
5
SO-8  
*N = Plastic DIP Package; SO = SOIC Package; T = T O-92 Package.  
REV. C  
–3–  
12345678

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