5秒后页面跳转
捷配首页

Datasheet > 转换器 > 模数转换器> AD678TD
AD678TD PDF预览

AD678TD

更新时间： 2024-01-03 02:14:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
14页 310K
描述
12-Bit 200 kSPS Complete Sampling ADC

阅读下载

获取价格

AD678TD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：CERAMIC, JLCC-44
针数：44Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.68最大模拟输入电压：18 V
最小模拟输入电压：-18 V最长转换时间：4.4 µs
转换器类型：ADC, FLASH METHODJESD-30 代码：S-CQCC-J44
JESD-609代码：e0长度：16.385 mm
最大线性误差 (EL)：0.024%标称负供电电压：-12 V
位数：12功能数量：1
端子数量：44最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5,+-12 V
认证状态：Not Qualified采样速率：0.2 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：3.43 mm
子类别：Analog to Digital Converters最大压摆率：34 mA
标称供电电压：12 V表面贴装：YES
技术：BIMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：16.385 mm
Base Number Matches：1

AD678TD 数据手册

 浏览型号AD678TD的Datasheet PDF文件第3页浏览型号AD678TD的Datasheet PDF文件第4页浏览型号AD678TD的Datasheet PDF文件第5页浏览型号AD678TD的Datasheet PDF文件第7页浏览型号AD678TD的Datasheet PDF文件第8页浏览型号AD678TD的Datasheet PDF文件第9页 
AD678  
PIN DESCRIPTION  
28-Lead DIP 44-Lead  
Symbol  
Pin No.  
JLCC Pin No. Type Name and Function  
AGND  
AIN  
BIPOFF  
7
6
10  
11  
10  
15  
P
AI  
AI  
Analog Ground. This is the ground return for AIN only.  
Analog Signal Input.  
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary  
output coding. Connect to REFOUT through 50 Ω resistor for 5 V input bipolar mode  
and twos complement binary output coding. See Figures 7 and 8.  
Chip Select. Active LOW.  
CS  
DGND  
4
14  
6
23  
DI  
P
Digital Ground  
DB11–DB4  
26–19  
40, 39, 37, 36, DO  
35, 34, 33, 31  
Data Bits 11 through 4. In 12-bit format (see 12/8 pin), these pins provide the upper 8 bits  
of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/L pin).  
Active HIGH.  
DB3, DB2  
18, 17  
16  
30, 27  
DO  
Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2.  
Active HIGH. In 8-bit format they are undefined and should be tied to VDD  
In 12-bit format, Data Bit 1. Active HIGH.  
.
DB1 (R/L)  
DB0 (HBE) 15  
EOC  
26  
25  
42  
DO  
DO  
DO  
In 12-bit format, Data Bit 0. Active HIGH.  
27  
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the  
conversion is finished. In asynchronous mode, EOC is an open drain output and  
requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC pins for information  
on EOC gating.  
EOCEN  
HBE (DB0) 15  
1
1
25  
DI  
DI  
End-Of-Convert Enable. Enables EOC pin. Active LOW.  
In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output  
contains low byte.  
OE  
2
3
DI  
Output Enable. The falling edge of OE enables DB11–DB0 in 12-bit format and  
DB11–DB4 in 8-bit format. Gated with CS. Active LOW.  
Reference Input. +5 V input gives 10 V full-scale range.  
+5 V Reference Output. Tied to REFIN through 50 Ω resistor for normal operation.  
In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field.  
Tied to VDD for right-justified output and tied to DGND for left-justified output.  
Start Convert. Active LOW. See SYNC pin for gating.  
SYNC Control. If tied to VDD (synchronous mode), SC, EOC and EOCEN are gated  
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS,  
and EOC is an open drain output. EOC requires an external 3 kΩ pull-up resistor in  
asynchronous mode.  
REFIN  
REFOUT  
R/L (DB1)  
9
8
16  
14  
12  
26  
AI  
AO  
DI  
SC  
SYNC  
3
13  
5
21  
DI  
DI  
VCC  
VEE  
VDD  
12/8  
11  
5
28  
12  
17  
8
43  
19  
P
P
P
DI  
+12 V Analog Power.  
–12 V Analog Power.  
+5 V Digital Power.  
Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied  
LOW, sets output format to 8-bit multiplexed.  
No Connect  
2, 4, 7, 9, 13,  
16, 18, 20, 22,  
24, 28, 29, 32,  
38, 41, 44  
These pins are unused and should be connected to DGND or VDD.  
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).  
All DO pins are three-state drivers; P = Power.  
PIN CONFIGURATIONS  
DIP PACKAGE  
JLCC PACKAGE  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
EOCEN  
OE  
V
DD  
EOC  
DB11  
DB10  
DB9  
DB8  
DB7  
DB6  
DB5  
DB4  
DB3  
6
5
4
3
2
44 43 42 41 40  
SC  
PIN 1  
NC  
7
8
39  
DB10  
NC  
IDENTIFIER  
CS  
V
EE  
38  
37  
36  
V
EE  
DB9  
DB8  
NC  
9
AIN  
10  
11  
AIN  
AD678  
TOP VIEW  
AD678  
TOP VIEW  
(Not to Scale)  
35  
34  
DB7  
DB6  
DB5  
NC  
AGND  
AGND  
REF  
12  
13  
14  
15  
OUT  
NC  
REF  
OUT  
33  
32  
31  
30  
REF  
IN  
REF  
IN  
BIPOFF 10  
11  
DB4  
BIPOFF  
NC  
16  
17  
DB3  
NC  
V
CC  
V
CC  
29  
12/8 12  
17 DB2  
16  
18 19 20 21 22 23 24 25 26 27 28  
13  
14  
SYNC  
DGND  
DB1 (R/L)  
15 DB0 (HBE)  
NC = NO CONNECT  
–6–  
REV. C  
1...3456789...14

下载PDF

与AD678TD相关器件

型号 品牌 描述 获取价格 数据表
AD678TD/883B ADI 12-Bit 200 kSPS Complete Sampling ADC

获取价格
AD678TJ ETC Analog-to-Digital Converter， 12-Bit

获取价格
AD678TJ/883B ETC Analog-to-Digital Converter， 12-Bit

获取价格
AD679 ADI 14-Bit 128 kSPS Complete Sampling ADC

获取价格
AD679* ETC 14-Bit 128 kSPS Complete Sampling ADC

获取价格
AD679_04 ADI 14-Bit 128 kSPS Complete Sampling ADC

获取价格

与AD678TD相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证