Datasheet > AD671

AD671

更新时间： 2022-11-29 04:20:07

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
16页	486K
描述
Monolithic 12-Bit 2 MHz A/D Converter

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AD671 数据手册

AD671–SPECIFICATIONS

_MINto T_MAX, with V_CC= +5 V

5%, V_REF= +5.000 V, unless otherwise noted)

؎ 5%, V_LOGIC= +5 V ؎ 10%, V_EE= –5 V

DIGITAL SPECIFICATIONS ⁽_؎^{For all grades T}

LOGIC INPUT

High Level Input Voltage

Low Level Input Voltage

High Level Input Current (V_IN= V_LOGIC

Low Level Input Current (V_IN= 0 V)

Input Capacitance

V_IH

V_IL

I_IH

I_IL

µA

)

C_IN

LOGIC OUTPUTS

High Level Output Voltage (I_OH= 0.5 mA)

Low Level Output Voltage (I_OL= 1.6 mA)

Output Capacitance

V_OH

V_OL

C_OUT

Specifications shown in

are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max

specifications are guaranteed, although only those shown in boldface are tested.

Specifications subject to change without notice.

_MINto T_MAXwith V_CC= +5 V

؎ 5%, V_IL= 0.8 V, V_IH= 2.0 V, V_OL= 0.4 V and V_OH= 2.4 V)

5%, V_LOGIC= +5 V

10%, V_EE= –5 V

SWITCHING SPECIFICATIONS ^{(For all grades T}

Conversion Time

(AD671-500)

(AD671-750)

t_C

475

725

ENCODE Pulse Width High

(AD671-500)

(AD671-750)

ENCODE Pulse Width Low

DAV Pulse Width

t_ENC

t_ENCL

(AD671-500)

(AD671-750)

ENCODE Falling Edge Delay

Start New Conversion Delay

Data and OTR Delay from DAV Falling Edge

Data and OTR Valid before DAV Rising Edge

t_DAV

t_F

200

300

t_R

t_DD

t_SS

NOTES

¹t_DDis measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.

²t_SSis measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.

b. Encode Pulse LOW

a. Encode Pulse HIGH

Figure 1. AD671 Timing Diagrams

REV. B

–4–

1 2 345 6 7...16

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