Datasheet > AD6644_17

AD6644_17

更新时间： 2022-02-26 12:11:28

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
25页	738K
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Analog-to-Digital Converter

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AD6644_17 数据手册

AD6644

DIGITAL SPECIFICATIONS

AV_CC= 5 V, DV_CC= 3.3 V; T_MIN= −25°C, T_MAX= +85°C, unless otherwise noted.

Table 2.

AD6644AST-40

AD6644AST-65

Parameter

Temp

Test Level¹

Unit

Min

Typ

Max

Min

Typ

Max

ENCODE

ENCODE INPUTS (ENCODE,

)

Differential Input Voltage²

Differential Input Resistance

Differential Input Capacitance

Full

25°C

0.4

V p-p

kΩ

2.5

LOGIC OUTPUTS (D13 to D0, DRY, OVR)

Logic Compatibility

Logic 1 Voltage³

CMOS

2.5

0.4

CMOS

2.5

0.4

Full

Logic 0 Voltage³

Output Coding

DMID

Twos complement

DV_CC/2

Twos complement

DV_CC/2

Full

¹See the Explanation of Test Levels section.

ENCODE

All ac specifications tested by driving ENCODE and

differentially. Reference Figure 18 for performance vs. encode power.

³Digital output logic levels: DV_CC= 3.3 V, C_LOAD= 10 pF. Capacitive loads >10 pF degrade performance.

SWITCHING SPECIFICATIONS

ENCODE

AV_CC= 5 V, DV_CC= 3.3 V; ENCODE and

= maximum conversion rate MSPS; T_MIN= –25°C, T_MAX= +85°C, unless otherwise noted.

Table 3.

AD6644AST-40

Typ Max

AD6644AST-65

Typ Max

Parameter

Temp

Full

Test Level¹

Unit

MSPS

Min

Maximum Conversion Rate

Minimum Conversion Rate

ENCODE Pulse Width High

ENCODE Pulse Width Low

6.5

¹See the Explanation of Test Levels section.

ENCODE

AV_CC= 5 V, DV_CC= 3.3 V; ENCODE and

unless otherwise noted.

= maximum conversion rate MSPS; T_MIN= −25°C, T_MAX= +85°C, C_LOAD= 10 Pf,

Table 4.

AD6644AST-40/65

Parameter

ENCODE INPUT PARAMETERS²

Name

Temp

Test Level¹

Unit

Min

Typ

Max

Encode Period @ 65 MSPS

Encode Period @ 40 MSPS

Encode Pulse Width High³@ 65 MSPS

Encode Pulse Width Low @ 65 MSPS

ENCODE/DATA READY

t_ENC

t_ENCH

t_ENCL

Full

15.4

7.7

6.2

9.2

Encode Rising to Data Ready Falling

Encode Rising to Data Ready Rising

@ 65 MSPS (50% Duty Cycle)

@ 40 MSPS (50% Duty Cycle)

ENCODE/DATA (D13:0), OVR

ENCODE to DATA Falling Low

ENCODE to DATA Rising Low

ENCODE to DATA Delay (Hold Time)⁴

ENCODE to DATA Delay (Setup Time)⁵

Encode = 65 MSPS (50% Duty Cycle)

Encode = 40 MSPS (50% Duty Cycle)

t_DR

t_{E_DR}

Full

2.6

3.4

t_ENCH+ t_DR

11.1

4.6

Full

10.3

15.1

12.3

17.1

15.9

t_{E_FL}

t_{E_RL}

t_{H_E}

t_{S_E}

Full

3.8

3.0

5.5

4.3

9.2

6.4

t_ENC− t_{E_FL}

9.8

19.4

Full

6.2

15.9

11.6

21.2

Rev. D | Page 4 of 24

1 2 3 456 7 8...25

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