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AD650JP

更新时间： 2024-02-27 01:38:41
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
12页 285K
描述
Voltage-to-Frequency and Frequency-to-Voltage Converter

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AD650JP 技术参数

Source Url Status Check Date：2013-05-01 14:56:15.722是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Not Recommended
零件包装代码：DIP包装说明：DIP, DIP14,.3
针数：14Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：8.26转换器类型：VOLTAGE TO FREQUENCY CONVERTER
JESD-30 代码：R-CDIP-T14JESD-609代码：e0
长度：19.43 mm最大线性误差 (EL)：0.005%
最大负输入电压：-10 V最大负电源电压：-18 V
最小负电源电压：-9 V标称负供电电压：-15 V
功能数量：1端子数量：14
最大工作频率：1 MHz最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED最大正输入电压：
电源：+-15 V认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Analog Special Function Converters
最大压摆率：8 mA最大供电电压：18 V
最小供电电压：9 V标称供电电压：15 V
表面贴装：NO技术：BIPOLAR
温度等级：MILITARY端子面层：Tin/Lead (Sn63Pb37)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

AD650JP 数据手册

 浏览型号AD650JP的Datasheet PDF文件第1页浏览型号AD650JP的Datasheet PDF文件第2页浏览型号AD650JP的Datasheet PDF文件第3页浏览型号AD650JP的Datasheet PDF文件第5页浏览型号AD650JP的Datasheet PDF文件第6页浏览型号AD650JP的Datasheet PDF文件第7页 
AD650  
CIRCUIT OPERATION  
UNIPOLAR CONFIGURATION  
The AD650 is a charge balance voltage-to-frequency converter. In  
the connection diagram shown in Figure 1, or the block diagram  
of Figure 2a, the input signal is converted into an equivalent cur-  
rent by the input resistance RIN. This current is exactly balanced  
by an internal feedback current delivered in short, timed bursts  
from the switched 1 mA internal current source. These bursts of  
current may be thought of as precisely defined packets of charge.  
The required number of charge packets, each producing one  
pulse of the output transistor, depends upon the amplitude of  
the input signal. Since the number of charge packets delivered  
per unit time is dependent on the input signal amplitude, a linear  
voltage-to-frequency transformation will be accomplished. The  
frequency output is furnished via an open collector transistor.  
Figure 2b. Reset Mode  
Figure 2c. Integrate Mode  
A more rigorous analysis demonstrates how the charge balance  
voltage-to-frequency conversion takes place.  
A block diagram of the device arranged as a V-to-F converter is  
shown in Figure 2a. The unit is comprised of an input integra-  
tor, a current source and steering switch, a comparator and a  
one-shot. When the output of the one-shot is low, the current  
steering switch S1 diverts all the current to the output of the op  
amp; this is called the Integration Period. When the one-shot  
has been triggered and its output is high, the switch S1 diverts  
all the current to the summing junction of the op amp; this is  
called the Reset Period. The two different states are shown in  
Figure 2 along with the various branch currents. It should be  
noted that the output current from the op amp is the same for  
either state, thus minimizing transients.  
Figure 2d. Voltage Across CINT  
The positive input voltage develops a current (IIN = VIN/RIN)  
which charges the integrator capacitor CINT. As charge builds up  
on CINT, the output voltage of the integrator ramps downward  
towards ground. When the integrator output voltage (Pin 1)  
crosses the comparator threshold (–0.6 volt) the comparator  
triggers the one shot, whose time period, tOS is determined by  
the one shot capacitor COS  
.
Specifically, the one shot time period is:  
tOS = COS × 6.8 ×103 sec/F + 3.0 ×10–7 sec  
(1)  
The Reset Period is initiated as soon as the integrator output  
voltage crosses the comparator threshold, and the integrator  
ramps upward by an amount:  
dV  
tOS  
∆V = tOS  
•
=
1mA– I  
(
)
(2)  
N
dt CINT  
After the Reset Period has ended, the device starts another Inte-  
gration Period, as shown in Figure 2, and starts ramping downward  
again. The amount of time required to reach the comparator  
threshold is given as:  
Figure 1. Connection Diagram for V/F Conversion,  
Positive Input Voltage  
t
OS/CINT(1mA – IIN )  
1mA  
IIN  
∆
–1  
V
(3)  
TI =  
=
= tOS  
dV  
dt  
IN/CINT  
The output frequency is now given as:  
IIN  
+ TI tOS ×1mA  
V
IN/RIN  
1
F Hz  
•
A
fOUT  
=
=
= 0.15  
(4)  
COS + 4.4 ×10–11  
F
tOS  
Note that CINT, the integration capacitor has no effect on the  
transfer relation, but merely determines the amplitude of the  
sawtooth signal out of the integrator.  
One Shot Timing  
A key part of the preceding analysis is the one shot time period  
that was given in equation (1). This time period can be broken  
down into approximately 300 ns of propagation delay, and a sec-  
ond time segment dependent linearly on timing capacitor COS  
When the one shot is triggered, a voltage switch that holds Pin 6  
.
Figure 2a. Block Diagram  
–4–  
REV. C  
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