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AD637JR PDF预览

AD637JR

更新时间: 2024-02-25 00:35:14
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
10页 163K
描述
High Precision, Wide-Band RMS-to-DC Converter

AD637JR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERDIP-14
针数:14Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.08Is Samacsys:N
转换器类型:RMS TO DC CONVERTERJESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.43 mm
最大线性误差 (EL):0.05%最大负电源电压:-18 V
最小负电源电压:-3 V标称负供电电压:-15 V
功能数量:1端子数量:14
最大工作频率:0.15 MHz最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED最大正输入电压:7 V
电源:+-15 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Analog Special Function Converters
最大压摆率:3 mA最大供电电压:18 V
最小供电电压:3 V标称供电电压:15 V
表面贴装:NO温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大总误差:0.7%
宽度:7.62 mmBase Number Matches:1

AD637JR 数据手册

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AD637  
100  
10  
100  
10  
BUFFER  
AD637  
RMS  
BUFFER  
OUTPUT  
OUTPUT  
BUFFER INPUT  
1
14  
SIGNAL  
INPUT  
NC  
ABSOLUTE  
VALUE  
13  
2
3
ANALOG COM  
+
12 NC  
11  
C3  
BIAS  
SECTION  
1.0  
1.0  
OUTPUT  
OFFSET  
SQUARER/DIVIDER  
+V  
S
4
5
25k⍀  
VALUES FOR C AND  
AV  
CHIP  
SELECT  
–V  
S
10  
1% SETTLING TIME  
0.1  
0.1  
FOR STATED % OF READING  
AVERAGING ERROR*  
ACCURACY ؎2% DUE TO  
COMPONENT TOLERANCE  
25k⍀  
DENOMINATOR  
INPUT  
9
+
6
7
* %dc ERROR + %RIPPLE (Peak)  
C
AV  
FILTER  
0.01  
8
0.01  
100k  
dB  
1
10  
100  
1k  
10k  
INPUT FREQUENCY – Hz  
Figure 9a.  
R
24k⍀  
X
24k⍀  
100  
10  
100  
VALUES OF C , C2 AND  
AV  
+
C2  
FOR 1 POLE  
FILTER, SHORT  
AND  
1% SETTLING TIME FOR  
STATED % OF READING  
AVERAGING ERROR*  
R
X
REMOVE C3  
FOR 1 POLE POST FILTER  
10  
* %dc ERROR + % PEAK RIPPLE  
ACCURACY ؎20% DUE TO  
COMPONENT TOLERANCE  
Figure 8. Two Pole Sallen-Key Filter  
Figure 9a shows values of CAV and the corresponding averaging  
error as a function of sine-wave frequency for the standard rms  
connection. The 1% settling time is shown on the right side of  
the graph.  
1.0  
1.0  
Figure 9b shows the relationship between averaging error, signal  
frequency settling time and averaging capacitor value. This  
graph is drawn for filter capacitor values of 3.3 times the averag-  
ing capacitor value. This ratio sets the magnitude of the ac and  
dc errors equal at 50 Hz. As an example, by using a 1 µF averag-  
ing capacitor and a 3.3 µF filter capacitor, the ripple for a 60 Hz  
input signal will be reduced from 5.3% of reading using the  
averaging capacitor alone to 0.15% using the single pole filter.  
This gives a factor of thirty reduction in ripple and yet the set-  
tling time would only increase by a factor of three. The values of  
CAV and C2, the filter capacitor, can be calculated for the desired  
value of averaging error and settling time by using Figure 9b.  
0.1  
0.1  
0.01  
100k  
0.01  
1
10  
100  
1k  
10k  
INPUT FREQUENCY – Hz  
Figure 9b.  
100  
10  
100  
10  
VALUES OF C , C2 AND C3  
AV  
AND 1% SETTLING TIME FOR  
STATED % OF READING  
AVERAGING ERROR*  
2 POLL SALLEN-KEY FILTER  
* %dc ERROR + % PEAK RIPPLE  
ACCURACY ؎20% DUE TO  
COMPONENT TOLERANCE  
The symmetry of the input signal also has an effect on the mag-  
nitude of the averaging error. Table I gives practical component  
values for various types of 60 Hz input signals. These capacitor  
values can be directly scaled for frequencies other than 60 Hz,  
i.e., for 30 Hz double these values, for 120 Hz they are halved.  
1.0  
1.0  
0.1  
0.1  
For applications that are extremely sensitive to ripple, the two pole  
configuration is suggested. This configuration will minimize  
capacitor values and settling time while maximizing performance.  
0.01  
100k  
0.01  
1
10  
100  
1k  
10k  
Figure 9c can be used to determine the required value of CAV  
C2 and C3 for the desired level of ripple and settling time.  
,
INPUT FREQUENCY – Hz  
Figure 9c.  
–6–  
REV. E  

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